SDR Technology

The different components of a radio system are illustrated in Fig. 2. Of course, all of the digital components may not be programmable, but the bigger the programmable part (dsp/fpga part on Fig. 2), the more software the radio. Dedicated ips1 are needed, for these ip it is more suitable to use the term configurable than programmable. In a typical sdr, the analog part is limited to a frequency translation down to an intermediate band which is sampled and all the signal processing is done digitally.

SDR Forum Classification

To encourage a common meaning for the term “sdr” the sdr Forum (renamed Wireless Innovation Forum proposes to distinguish five tiers:

• Tier 0 – Hardware Radio: The radio parameters cannot be changed, radio is implemented only with hardware components.
• Tier 1 – Software Controlled Radio: A radio where only the control functions are implemented in software, baseband processing is still performed in hardware, the radio is able to switch between different hardware.
• Tier 2 – Software-Defined Radio: The most popularly understood definition of sdr: the radio includes software control of modulation, bandwidth, frequency range and frequency bands. Conversion to digital domain still occurs after frequency conversion. It is currently implemented using a wide range of technologies: Asics, fpgas, dsps, etc.
• Tier 3 – Ideal Software Radio: Digital conversion occurs directly at the antenna, programmability extends to the whole system.
• Tier 4 – Ultimate Software Radio: Same reconfigurability capabilities as in Tier 3, but with a switching between two configurations in less than one millisecond.

The main restriction to build an ideal software radio is sampling rate: sampling at a high rate is not an easy task. Following the Shannon-Nyquist theorem, sampling the rf signal at a rate greater than twice the frequency of the signal is sufficient to reconstruct the signal. Sampling can be done at lower rate (decimation), but errors can be introduced (aliasing) that can be corrected by filtering (dirty radio concept). Building an sdr terminal implies a trade-of between sampling frequency and terminal complexity. For instance, sampling at 4.9 GHz would require a 12-bit resolution adc with at least 10GHz sample rate which is today not available with reasonable power consumption (several hundreds Watt).

Cognitive Radio

sdr technology enables over the air programming (Otap) which consists in describing methods for distributing new software updates through the radio interface. However, as sdr architectures are heterogeneous, a standard distribution method has not emerged yet.

Cognitive Radio is a wireless communication system that can sense the air, and decide to configure itself in a given mode, following a local or distributed decision algorithm. Although Tier 3 sdr would be an ideal platform for cognitive radio implementation, cognitive radios do not have to be sdr.

Cognitive Radio is currently a very hot research topic as show the dozens of sessions in research conferences dedicated to it. In 2009, the American National Science Foundation (nsf) held a workshop on “Future Directions in Cognitive Radio Network Research”  28. The purpose of the workshop was to explore how the transition from cognitive radios to cognitive radio networks can be made. The resulting report indicated the following: 

The report also mentioned the lack of cognitive radio testbeds and urged “The development of a set of cognitive networking test-beds that can be used to evaluate cognitive networks at various stages of their development”, which, in some sense strengthens the creation of the Socrate team and its involvement in the FIT project  23.

7.1.1 FloPoCo

• Name:
  Floating-Point Cores, but not only
• Keyword:
  Synthesizable VHDL generator
• Functional Description:
  The purpose of the open-source FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm.
• URL:
  http://­flopoco.­org
• Contact:
  Florent de Dinechin
• Participants:
  Florent de Dinechin, Luc Forget
• Partners:
  ENS Lyon, Insa de Lyon, Inria, Fulda University of Applied Science

7.1.2 Sytare

• Keywords:
  Embedded systems, Operating system, Non volatile memory
• Functional Description:
  Sytare is an embedded operating system targeting tiny platforms with intermittent power. In order to make power failures transparent for the application, the system detects imminent failures and saves a checkpoint of program state to non-volatile memory. Hardware peripherals are also made persistent without requiring developer attention.
• URL:
  https://­gitlab.­inria.­fr/­citi-lab/­sytare
• Publication:
  hal-01460699
• Authors:
  Tristan Delizy, Gautier Berthou, Guillaume Salagnac, Kevin Marquet, Tanguy Risset
• Contact:
  Guillaume Salagnac

7.1.3 NanoTracer

• Name:
  NanoTracer
• Keywords:
  Embedded systems, Power monitoring, Low power consumption
• Functional Description:
  NanoTracer is a high performance ammeter dedicated to power measurements for small devices. The system measures currents between 100nA and 100mA (gain is audo-adjusted dynamically) with a sampling frequency of 2Msps. Data is streamed to a PC over USB which enables long-running experiments, or just real-time visualization of data.
• URL:
  https://­geromueller.­de/­nanotracer/
• Contact:
  Guillaume Salagnac

7.1.4 marto

• Name:
  Modern Arithmetic Tools
• Keywords:
  High-level synthesis, Arithmetic, FPGA
• Functional Description:

  Marto provides C++ headers to implement custom sized arithmetic operators such as:

  Custom sized posits and their environment (including the quire) Custom sized IEEE-754 numbers Custom sized Kulisch accumulators (and sums of products)

• URL:
  https://­gitlab.­inria.­fr/­lforget/­marto
• Publication:
  hal-02130912v4
• Contact:
  Yohann Uguen
• Participants:
  Yohann Uguen, Florent de Dinechin, Luc Forget

7.1.5 hint

• Name:
  High-level synthesis Integer Library
• Keyword:
  High-level synthesis
• Functional Description:
  Hint is an header-only arbitrary size integer API with strong semantics for C++. Multiple backends are provided using various HLS libraries, allowing a user to write one operator and synthetize it using the main vendor tools.
• URL:
  https://­github.­com/­yuguen/­hint
• Publication:
  hal-02131798v2
• Contact:
  Luc Forget
• Participants:
  Yohann Uguen, Florent de Dinechin, Luc Forget

7.1.6 Syfala

• Name:
  Low-Latency Synthesizer on FPGA
• Keywords:
  FPGA, Compilers, High-level synthesis, Audio signal processing
• Functional Description:

  The goal of Syfala is to design an FPGA-based platform for multichannel ultra-low-latency audio Digital Signal Processing programmable at a high-level with Faust and usable for various applications ranging from sound synthesis and processing to active sound control and artificial sound field/room acoustics.

  A series of tools are currently being developed around SyFaLa. While none of them has been officially released yet, you can follow their development/evolution on the project Git repository: https://gitlab.inria.fr/risset/syfala

• URL:
  https://­faust.­grame.­fr/­syfala/
• Contact:
  Tanguy Risset

8.1.1 Wake-Up radio and wireless power transfer

A large survey on Energy Harvesting architectures and used diodes with a large set of simulations to evaluate the impact of the chosen frequency band was published 7. This survey was used to develop a new solution to build a completely autonomous Wake-Up radio device using Energy Harvesting to feed the Wake-Up circuit 6. In parallel, we have started the ANR project U-Wake, dedicated to build an autonomous Wake-Up device based on artificial neural networks. We also have continued our work on optimizing the waveform for optimal Wireless Power Transfer (WPT).

8.1.2 RFID

To integrate RFID capabilities in textiles, we proposed an alternative to the current RFID yarn solution with the use of an antenna having a helical geometry that answers to the mechanical issues and keeps quite similar electrical and radiative properties with respect to the present solution. The RFID helical tag was designed and simulated taking into consideration the constraints of the manufacturing process. The helical RFID tag was then fabricated using the E-Thread® technology and experimental characterization showed that the obtained structure exhibited good performance with 10.6 m of read range in the ultra high frequency (UHF) RFID band and 10 percents of tolerance in terms of elongation 38. For tag-to-tag communications, we proposed a source orientation optimization to increase the modulation depth and therefore to reduce the bit-error-rate between two tags 12.

8.1.3 Combination of spatial modulation and full-duplex

To increase the realism of our proposed combination of Spatial Modulation and Full-Duplex techniques 16, we have studied the impact of RF non-idealities, and particularly the impact of the Power Amplifier nonlinearities 13. A solution to reduce this impact was proposed.

8.1.4 Other related works

Several works have been performed focusing on the FM RDS technology 4, 11, 14. More precisely, by employing the Radio Data System (RDS) protocol of a local Frequency Modulation (FM) transmission, road traffic's dangerous areas (rail crossing, unmarked crossroads, etc.) could be announced. The code of a warning message is broadcasted in the close vicinity of the dangerous area and, at the receiver side, a corresponding image is displayed on the car's tablet PC.

8.3.1 Ultra-low latency audio on FPGA

The complete faust2FPGA studied in future FAST ANR project. The central flow has been prototyped and presented in .

Socrate and GRAME have started a collaboration through the Syfala(synthèse audio faible latence). whose goal is to design an FPGA-based platform for multichannel ultra-low-latency audio Digital Signal Processing, programmable at high-level with Faust and using Socrate's software FloPoCo. A first very preliminary version of this compiler was presented at IFC2020  27 (see Fig. 4). Then an ANR project was launched in March 2021 (FAST: Fast Audio Signal-processing Technologies on FPGA). This topic became the first research axis of the new Emeraude Team.

8.3.2 Administrative creation of Emeraude

At time of writing, the creation of the Emeraude team has been validated by the Scientific Committee of Inria Lyon. It is already started as an Insa Team, a convention between Grame, Insa-Lyon and Inria has been signed. Emeraude should become the first Inria team created in the new Inria Lyon Center. In June, Romain Michon, researcher at Grame was hired as ISFP at Inria to reinforce the Emeraude project.

The emeraude team proposes to study embedded programmable audio systems. In particular, it is involved in the developpement and distribution of the Faust Language. The four research axis proposed by Emeraude are:

• Ultra-Low Audio Latency on FPGA
• Advanced Arithmetics for Digital Audio
• Digital Audio Signal Processing
• Language, Compilation, Deployment, and Interfaces for Audio Signal Processing

8.4.1 Towards Arithmetic-Centered Filter Design

Linear-time invariant (LTI) digital filters are usually specified in the frequency domain. Linearity is at the core of Fourier transforms and other techniques allow us to design time-domain implementions from a frequency-domain specification. However, actual (finite-precision) implementations of LTI filters, in particular recursive ones, are necessarily no longer linear due to rounding errors. This leads to unwanted effects such as limit cycle oscillations. As a nice side effect of this definition, filter design and implementation become a single well-founded global optimisation problem. Existing tools to solve this problem are reviewed and the missing ones are framed.

8.4.2 Lossless Differential Table Compression for Hardware Function Evaluation

Hsiao et al. recently introduced, in the context of multipartite table methods, a lossless compression technique that replaces a table of numerical values with two smaller tables and one addition. 5 shows that this technique has many more applications than originally published, and that in many of these applications the addition is for free in practice. It also improves this technique and the resulting architecture by exposing a wider implementation space, and an exhaustive but fast algorithm exploring this space. These contributions are implemented in the open-source FloPoCo core generator and evaluated on FPGA and ASIC, reducing area up to a factor 2.

8.4.3 Resource Optimal Truncated Multipliers for FPGAs

In contrast to application specific integrated circuits (ASICs), FPGAs impose some distinct challenges in multiplier design due to many possibilities of computing the partial products using logic-based or DSP-based sub-multipliers. To tackle this, 9 extends to truncated multipliers a previously proposed tiling methodology which translates the multiplier design into a geometrical tiling problem. The tiling with the least resources guaranteeing last-bit accuracy can be found with integer linear programming (ILP). Compared to previous approaches that use a fixed number of guard bits or optimize at the level of the dot diagrams, this allows a much better use of sub-multipliers resulting in significant area savings without sacrificing the timing.

Research Contract with Bosch 2021

In collaboration with Aric, Socrate worked with Bosch on the implementation of the square root function the context of an embedded processor.

Insa-Spie IoT Chair

The Insa-Spie IoT Chair  relies on the expertise of the CITI Lab. The skills developed within the different teams of the lab integrate the study, modelling, conception and evaluation of technologies for communicating objects and dedicated network architectures. It deals with network, telecom and software matters as well as societal issues such as privacy. The chair will also lean on the skills developed at INSA Lyon or in IMU LabEx.

Inria Project Lab: ZEP

The ZEP project addresses the issue of designing tiny computing objects with no battery by combining non-volatile memory (NVRAM), energy harvesting, micro-architecture innovations, compiler optimizations, and static analysis. The main application target is Internet of Things (IoT) where small communicating objects will be composed of this computing part associated to a low-power wake-up radio system. The ZEP project gathers four INRIA teams that have a scientific background in architecture, compilation, operating system and low power together with the CEA Lialp and Lisan laboratories of CEA LETI & LIST.

                

The scientific work (in progress) is organized around three fields :

• specific NVRAM-based architecture
• dedicated compiler pass that computes a worst-case energy consumption
• operating system managing NVRAM and energy, ensuring memory consistency across power outages

The project is illustrated by the figure 5, where PACAP, SOCRATE, CORSE, and CAIRN are the teams involved in the project.

ANR - Imprenum

The objective of this project (INSA-Lyon, École Normale Supérieure de Lyon, CEA LETI) is to promote accuracy as a first class concern in all the levels of a computing system:

• at the hardware level, with better support for lower-than-standard and higher-than-standard precisions;
• at the level of run-time support software, in particular answering the memory management challenges entailed by adaptive precision;
• at the lower level of mathematical libraries (kernel level), for instance BLAS for linear algebra, enhancing well established libraries with precision and accuracy control;
• at the higher level of mathematical libraries (solver level, including algebraic linear solvers such as LAPACK, ad hoc steppers for Ordinary Differential Equation, eigenvalues kernels, triangularization problems for computational geometry, etc.) Here, accuracy and precision control of the lower levels should enable higher-level properties such as convergence and stability;
• at the compiler level, enhancing optimising compilers with novel optimisations related to precision and accuracy;
• at the language level, embedding accuracy specification and control in existing languages, and possibly defining domain-specific languages with accuracy-aware semantics for some classes of applications.

ANR FAST

The main objective of The FAST ANR project started in March 2021 is to develop a new Faust architecture backend for FPGA-based platforms. One of the challenges here is the optimization of the module generated by Faust. The real breakthrough will be obtained with the use of two recent technologies in the Faust compilation workflow:

• High Level Synthesis (HLS) for compiling Faust program to VHDL
• fixed-point support in the code generated by the Faust compiler, building on the expertise developed at CITI around the FloPoCo project. Eventually, we aim at generating VHDL code directly from the Faust compiler.

This type of system has a wide range of applications in multiple domains. As mentioned earlier, music technology is in high demand for low latency because it helps increasing the playability of musical instruments on stage. Hence, the platform developed as part of FAST will be used to design programmable digital musical instruments and effect processors. In that context, the computational power of the FPGA will be exploited to run complex algorithms (e.g., physics-based models of musical instruments, modal reverbs, etc.) that are too costly to run on a traditional platform (i.e., laptop, etc.).

ADT FFF

The objective of this ADT is to continue the engineering support for the development of the Syfala tools for the compilation from high level languages (C, Faust) to FPGA for audio signal processing applications.

This work will be done in the forthcoming Emeraude Inria team and the engineer will be a very important support for the tool development in the team (Syfala of course but also FloPoCo or Faust for instance).

Digital Hardware AI Architectures

Florent de Dinechin participates to the chair Digital Hardware AI Architectures held by Prof. Frédéric Pétrot at the Multidisciplinary Institute in Artificial Intelligence (MIAI) of Grenoble. The other participants are François Duhem (Spintec/CEA) and Fabrice Rastello (LIG/Inria), with industrial partners Google France, Kalray, STMicroelectronics, and Upmem.

This chair funds the PhD of Maxime Christ, which studies how very low-precision arithmetic formats may improve the efficiency of the learning phase of neural networks.

ANR - U-WAKE

Our U-Wake project aims to achieve a breakthrough in the field of IoT by developing a disruptive wake-up receiver solution based on (1) a bioinspired architecture achieved with an industrial CMOS technology (with transistors operating in deep sub-threshold regime) and (2) ElectroMagnetic energy harvesting. The originality lies in the association of a Radio Frequency (RF) demodulator to a neuro-inspired detector [2] [3] and data-processing through a spiking neural network (SNN), resulting in a complete ultra-low power wake-up radio supplied with a voltage of a few 100 mV.

CIG Project IMMUNet

The IMMUNet (Industrial Machine Monitoring Unplugged Network) innovation allows to effectively sense the current condition and track the activities of the industrial machines in real time. IMMUNet comprises miniature (1-2 cm2) tags and one or several gateways (GWs) controlling the network and collecting the data. The tags can be powered with a battery, by collecting the energy from the environment or through delivering the energy wirelessly. A tag is equipped with one or multiple sensors (acceleration, temperature, etc.) and has memory to store the relevant technical information about the machine, its activities, and environment. The dependable connectivity between the tags and the GWs is automatically established and maintained through the ultra energy-efficient wireless connectivity protocol based on a combination of time and frequency multiple access (TDMA and FDMA) schemes implemented by GWs and tags firmware. The protocol operates on top of LoRa-modulated radio-signals transmitted in the 2.4 GHz frequency band, allowing the solution to be used anywhere around the globe. In case of poor connectivity, multi-hop transmissions can also be enabled.

Member of the editorial boards

• Florin Hutu and Guillaume Villemaud are Topical Advisory Panel Members of the MDPI Sensors.

Reviewer - reviewing activities

• Florin Hutu was a reviewer for the following journals: IEEE Transactions on Green Communications and Networking, IEEE Journal of RFID, IEEE Sensor Letters, MDPI Energies, MDPI Sensors, MDPI Signals.
• Florent de Dinechin was a reviewer for the following journals: ACM Transactions on Reconfigurable Technology and Systems, IEEE Transactions on Computers, IEEE Transactions on Emerging Topics in Computing, AEÜ - International Journal of Electronics and Communications.

11.1.1 Teaching

• Tanguy Risset is professor at the Telecommunications Department of Insa Lyon.
• Florent de Dinechin is a professor at the Computer Science Department of Insa Lyon. He also teaches computer architecture at ENS-Lyon.
• Guillaume Salagnac and Kevin Marquet are associate professors at the Computer Science Department of Insa Lyon.
• Guillaume Villemaud and Florin Hutu are associate professors at the Electrical Engineering Department of Insa Lyon.

11.1.2 Supervision

• PhD defended in 2021: Gautier Berthou : Operating system for transiently powered systems, Inria, (IPL ZEP) since 01/2018.
• PhD defended in 2021 :Yanni Zhou : Full Duplex and spatial modulation since 10/2018
• PhD in progress : Luc Forget : Algèbre linéaire calculant au plus juste, ANR Imprenum, since 10/2018.
• PhD in progress : Tarik Lassouaoui : Tag 2 Tag communication since 10/2018
• PhD in progress : Regis Rousseau : Wireless Power Transfer since 10/2018
• PhD in progress : Maxime Christ : Learning in Very Low Precision since 10/2018
• PhD starting : Maxime Popoff : Compilation of Audio Program on FPGA since 10/2020

11.1.3 Juries

• Tanguy Risset was a member of the jury of the following theses:
  • Thomas Baumela (reviewer, U. Grenoble)
  • Arash Shafiei (reviewer and jury president, U. Grenoble)

International journals

• 3 articleS.Sofia Benouakta, F.Florin Hutu and Y.Yvan Duroc. Stretchable Textile Yarn Based on UHF RFID Helical Tag.Textiles13November 2021, 547- 557
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• 4 articleR. G.Radu Gabriel Bozomitu, F. D.Florin Doru Hutu and N.Nicolas De Pinho Ferreira. Drivers’ Warning Application Through Image Notifications on the FM Radio Broadcasting Infrastructure.IEEE Access9January 2021, 13553 - 13572
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• 5 articleM.Maxime Christ, L.Luc Forget and F.Florent de Dinechin. Lossless Differential Table Compression for Hardware Function Evaluation.IEEE Transactions on Circuits and Systems II: Express BriefsNovember 2021
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• 6 articleA.Achille Fumtchum, F. D.Florin Doru Hutu, P.Pierre Tsafack, G.Guillaume Villemaud and E.Emmanuel Tanyi. Towards a Battery-Free Wake-Up Radio.ElectronicsOctober 2021, 1-12
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• 7 articleA.Achille Fumtchum, P.Pierre Tsafack, F. D.Florin Doru Hutu, G.Guillaume Villemaud and E.Emmanuel Tanyi. A Survey of RF Energy Harvesting Circuits.International Journal of Innovative Technology and Exploring Engineering107May 2021, 99-106
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International peer-reviewed conferences

• 8 inproceedingsS.Sofia Benouakta, F.Florin Hutu and Y.Yvan Duroc. Passive UHF RFID Yarn For Temperature Sensing Applications.RFID-TA 2021 - 11th IEEE international Conference on RFID Technology and ApplicationsDehli, IndiaIEEEOctober 2021, 1-3
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• 9 inproceedingsA.Andreas Böttcher, M.Martin Kumm and F.Florent De Dinechin. Resource Optimal Truncated Multipliers for FPGAs.ARITH 2021 - 28th IEEE International Symposium on Computer ArithmeticTorino, ItalyIEEEJune 2021, 1-8
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• 10 inproceedingsF.Florent De Dinechin, S.-I.Silviu-Ioan Filip, M.Martin Kumm and A.Anastasia Volkova. Towards Arithmetic-Centered Filter Design.ARITH 2021 - 28th IEEE Symposium on Computer ArithmeticTorino, ItalyJune 2021, 1-4
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• 11 inproceedingsF. D.Florin Doru Hutu and R. G.Radu Gabriel Bozomitu. Driver's warning notifications by using FM RDS technology.ISSCS 2021 - International Symposium on Signals, Circuits and SystemsIasi, RomaniaJuly 2021, 1-4
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• 12 inproceedingsT.Tarik LASSOUAOUI, F.Florin Hutu, G.Guillaume Villemaud and Y.Yvan Duroc. Modulation Depth Enhancement for Randomly Arranged Tags in Passive RFID Tag to Tag Communications.RFID-TA 2021 - 11th IEEE International Conference on RFID Technology and ApplicationsDelhi, IndiaIEEEOctober 2021, 1-4
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• 13 inproceedingsY.Yanni Zhou, F.Florin Hutu, G.Guillaume Villemaud and T.Taneli Riihonen. Nonlinear Power Amplifier Effects on a Full Duplex Spatial Modulation System.PIMRC 2021 - IEEE 32nd Annual International Symposium on Personal, Indoor and Mobile Radio CommunicationsOulu / Virtual, FinlandIEEESeptember 2021, 1-5
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Conferences without proceedings

• 14 inproceedingsN.Nicolas De Pinho Ferreira and F. D.Florin Doru Hutu. Maquette pédagogique pour l'étude des transmissions Radio Data System.CETSIS 2021 - Colloque de l'Enseignement des Technologies et des Sciences de l'Information et des SystèmesValenciennes, FranceJune 2021
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Doctoral dissertations and habilitation theses

• 15 thesisG.Gautier Berthou. Operating system dedicated to NVRAM-based low power embedded systems.Université de LyonMarch 2021
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• 16 thesisY.Yanni Zhou. On the performance of spatial modulation and full Duplex radio architectures.Université de LyonDecember 2021
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