2023Activity reportProject-TeamTARAN

Moore’s Law is Running Out of Steam

The limits of traditional transistor process technology have been known for a long time. We are now approaching these limits while alternative technologies are still in early stages of development. The economical drive for more performance will persist, and we expect a surge in specialized architectures in the mid-term to squeeze performance out of CMOS technology. Use of Non-Volatile Memory (NVM), Processing-in-Memory (PIM), and various work on approximate computing are all examples of such architectures.

Specialization is the Common Denominator

Specialization, which has been a small niche in the past, is now widespread  56. The main driver today is energy efficiency—small embedded devices need specialized hardware to operate under power/energy constraints. In the next ten years, we expect specializations to become even more common to meet increasing demands for performance. In particular, high-throughput workloads traditionally run on servers (e.g., computational science and machine learning) will offload (parts of) their computations to accelerators. We are already seeing some instances of such specialization, most notably accelerators for neural networks that use clusters of nodes equipped with FPGAs and/or ASICs.

The Need for Abstractions

The main drawback of hardware specialization is that it comes with significant costs in terms of productivity. Although High-Level Synthesis tools have been steadily improving, design and implementation of custom hardware (HW) are still time consuming tasks that require significant expertise. As specializations become inevitable, we need to provide programmers with tools to develop specialized accelerators and explore their large design spaces. Raising the level of abstraction is a promising way to improve productivity, but also introduces additional challenges to maintain the same levels of performance as manually specified counterparts. Taking advantage of domain knowledge to better automate the design flow from higher level specifications to efficient implementations is necessary for making specialized accelerators accessible.

Language/Programming Model

This is the main interface to the programmer that has two (sometimes conflicting) goals. One is that the programmer should be able to concisely specify the computation. The other is that the domain knowledge of the programmer must also be expressed such that the other layers can utilize it.

Compiler

The compiler is an important component for both productivity and performance. It improves productivity by allowing the input language to be more concise by recovering necessary information through compiler analysis. It is also where the first set of analyses and transformations are performed to realize efficient custom hardware.

Runtime

Runtime complements adjacent layers with its dynamicity. It has access to more concrete information about the input data that static analyses cannot use. It is also responsible for coordinating various processing elements, especially in heterogeneous settings.

Hardware Design

There are many design knobs when building an accelerator: the amount/type of parallelism, communication and on-chip storage, number representation and computer arithmetic, and so on. The key challenge is in navigating through this design space with the help of domain knowledge passed through the preceding layers.

Emerging Technology

Use of non-conventional hardware components (e.g., NVM or optical interconnects) opens further avenues to explore specialized designs. For a domain where such emerging technologies make sense, this knowledge should also be taken into account when designing the HW.

Key Investigators:

E. Casseau, F. Charot, D. Chillet, S. Derrien, A. Kritikakou, B. Le Gal, P. Quinton, S. Rokicki, O. Sentieys.

Accelerators are custom hardware that primarily aim to provide high-throughput, energy-efficient, computing platforms. Custom hardware can give much better performance compared to more general architectures simply because they are specialized, at the price of being much harder to “program.” Accelerator designers need to explore a massive design space, which includes many hardware parameters that a software programmer has no control over, to find a suitable design for the application at hand.

Our first objective in this context is to further enlarge the design space and enhance the performance of accelerators. The second, equally important, objective is to provide the designers with the means to efficiently navigate through the ever-expanding design space. Cross-layer expertise is crucial in achieving these goals—we need to fully utilize available domain knowledge to improve both the productivity and the performance of custom hardware design.

Positioning

Hardware acceleration has already proved its efficiency in many datacenter, cloud-computing or embedded high-performance computing (HPC) applications: machine learning, web search, data mining, database access, information security, cryptography, financial, image/signal/video processing, etc. For example, the work at Microsoft in accelerating the Bing web search engine with large-scale reconfigurable fabrics has shown to improve the ranking throughput of each server by 95%  66, and the increasing need for acceleration of deep learning workloads  69.

Hardware accelerators still lack efficient and standardized compilation toolflows, which makes the technology impractical for large-scale use. Generating and optimizing hardware from high-level specifications is a key research area with considerable interest  57, 64. On this topic, we have been pursuing our efforts to propose tools whose design principles are based on a tight coupling between the compiler and the target hardware architectures.

Key Investigators:

S. Filip, S. Derrien, O. Sentieys, M. Traiola.

An important design knob in accelerators is the number representation—digital computing is by nature some approximation of real world behavior. Appropriately selecting the number representation that respects a given quality requirement has been a topic of study for many decades in signal/image processing: a process known as Word-Length Optimization (WLO). We are now seeing the scope of number format-centered approximations widen beyond these traditional applications. This gives us many more approximation opportunities to take advantage of, but introduces additional challenges as well.

Earlier work on arithmetic optimizations has primarily focused on low-level representations of the computation (i.e., signal-flow graphs) that do not scale to large applications. Working on higher level abstractions of the computation is a promising approach to improve scalability and to explore high-level transformations that affect accuracy. Moreover, the acceptable degree of approximation is decided by the programmer using domain knowledge, which needs to be efficiently utilized.

Positioning

Traditionally, fixed-point (FxP) arithmetic is used to relax accuracy, providing important benefits in terms of delay, power and area 7. There is also a large body of work on carefully designing efficient arithmetic operators/functions that preserve good numerical properties. Such numerical precision tuning leads to a massive design space, necessitating the development of efficient and automatic exploration methods.

The need for further improvements in energy efficiency has led to renewed interest in approximation techniques in the recent years  65. This field has emerged in the last years, and is very active recently with deep learning as its main driver. Many applications have modest numerical accuracy requirements, allowing for the introduction of approximations in their computations  58.

Key Investigators:

E. Casseau, D. Chillet, F. F. Dos Santos, A. Kritikakou, O. Sentieys, M. Traiola.

With advanced technology nodes and the emergence of new devices pressured by the end of Moore's law, manufacturing problems and process variations strongly influence electrical parameters of circuits and architectures  63, leading to dramatically reduced yield rates  67. Transient errors caused by particles or radiations will also more and more often occur during execution  70, 68, and process variability will prevent predicting chip performance (e.g., frequency, power, leakage) without a self-characterization at run time. On the other hand, many systems are under constant attacks from intruders and security has become of utmost importance.

In this research direction, we will explore techniques to protect architectures against faults, errors, and attacks, which have not only a low overhead in terms of area, performance, and energy 9, 8, 4, but also a significant impact on improving the resilience of the architecture under consideration. Such protections require to act at most layers of the design stack.

Key Investigators:

D. Chillet, S. Derrien, O. Sentieys, M. Traiola.

Domain specific accelerators have more exploratory freedom to take advantage of non-conventional technologies that are too specialized for general purpose use. Examples of such technologies include optical interconnects for Network-on-Chip (NoC) and Non-Volatile Memory (NVM) for low-power sensor nodes. The objective of this research direction is to explore the use of such technologies, and find appropriate application domains. The primary cross-layer interaction is expected from Hardware Design to accommodate non-conventional Technologies. However, this research direction may also involve Runtime and Compilers.

6.1.1 Gecos

• Name:
  Generic Compiler Suite
• Keywords:
  Source-to-source compiler, Model-driven software engineering, Retargetable compilation
• Scientific Description:
  The Gecos (Generic Compiler Suite) project is a source-to-source compiler infrastructure targeted at program transformations mainly for High-Level-Synthesis tools. Gecos uses the Eclipse Modeling Framework (EMF) as an underlying infrastructure. Gecos is open-source and is hosted on the Inria gitlab. The Gecos infrastructure is still under very active development and serves as a backbone infrastructure to several research projects of the group.
• Functional Description:
  GeCoS provides a programme transformation toolbox facilitating parallelisation of applications for heterogeneous multiprocessor embedded platforms. In addition to targeting programmable processors, GeCoS can regenerate optimised code for High Level Synthesis tools.
• News of the Year:
  With the recent work on the Speculative HLS project and the new ANR LOTR, we have extended the tool to integrate some new analysis and transformation based on the Circt project (https://circt.llvm.org). We are also moving toward generating verilog for a subset of input C code. The objective is to be able to generate hardware with a fully open-source toolchain.
• URL:
  https://­gitlab.­inria.­fr/­gecos
• Publication:
  hal-03714101
• Contact:
  Steven Derrien
• Participants:
  Simon Rokicki, Dylan Leothaud, Jean-Michel Gorius, Steven Derrien
• Partner:
  Université de Rennes 1

6.1.2 SmartSense

• Name:
  Sensor-Aided Non-Intrusive Load Monitoring
• Keywords:
  Wireless Sensor Networks, Smart building, Non-Intrusive Appliance Load Monitoring
• Functional Description:
  To measure energy consumption by equipment in a building, NILM techniques (Non-Intrusive Appliance Load Monitoring) are based on observation of overall variations in electrical voltage. This avoids having to deploy watt-meters on every device and thus reduces the cost. SmartSense goes a step further to improve on these techniques by combining sensors (light, temperature, electromagnetic wave, vibration and sound sensors, etc.) to provide additional information on the activity of equipment and people. Low-cost sensors can be energy-autonomous too.
• URL:
  https://­smartsense.­inria.­fr/
• Contact:
  Olivier Sentieys
• Participants:
  Olivier Sentieys, Guillermo Enrique Andrade Barroso, Mickael Le Gentil, Sonia Barrios Pereira

6.1.3 TypEx

• Name:
  Type Exploration Tool
• Keywords:
  Embedded systems, Fixed-point arithmetic, Floating-point, Low power consumption, Energy efficiency, FPGA, ASIC, Accuracy optimization, Automatic floating-point to fixed-point conversion
• Scientific Description:
  The main goal of TypEx is to explore the design space spanned by possible number formats in the context of High-Level Synthesis. TypEx takes a C code written using floating-point datatypes specifying the application to be explored. The tool also takes as inputs a cost model as well as some user constraints and generates a C code where the floating-point datatypes are replaced by the wordlengths found after exploration. The best set of wordlengths is the one found by the tool that respects the accuracy constraint given and that minimizes a parametrized cost function.
• Functional Description:
  TypEx is a tool designed to automatically determine custom number representations and word-lengths (i.e., bit-width) for FPGAs and ASIC designs at the C source level. TypEx is available open-source at https://gitlab.inria.fr/gecos/gecos-float2fix. See README.md for detailed instructions on how to install the software.
• URL:
  https://­gitlab.­inria.­fr/­gecos/­gecos-float2fix
• Contact:
  Olivier Sentieys
• Participants:
  Olivier Sentieys, Van Phu Ha, Tomofumi Yuki, Ali Hassan El Moussawi

6.2.1 MPTorch: a PyTorch-based framework for simulating custom precision DNN training

Participants: Silviu-Ioan Filip, Paul Estano.

Keywords: Computer architecture, Arithmetic, Custom Floating-point, Deep learning, Multiple-Precision

Scientific description: MPTorch is a wrapper framework built atop PyTorch that is designed to simulate the use of custom/mixed precision arithmetic in PyTorch, especially for DNN training.

Functional description: MPTorch reimplements the underlying computations of commonly used layers for CNNs (e.g. matrix multiplication and 2D convolutions) using user-specified floating-point formats for each operation (e.g. addition, multiplication). All the operations are internally done using IEEE-754 32-bit floating-point arithmetic, with the results rounded to the specified format.

• Contact: Silviu-Ioan Filip
• URL: mptorch on github

6.2.2 E-methodHW: an automatic tool for the evaluation of polynomial and rational function approximations

Participants: Silviu-Ioan Filip, Matei Istoan.

Keywords: function approximation, FPGA hardware implementation generator

Scientific description: E-methodHW is an open source C/C++ prototype tool written to exemplify what kind of numerical function approximations can be developed using a digit recurrence evaluation scheme for polynomials and rational functions.

Functional description: E-methodHW provides a complete design flow from choice of mathematical function operator up to optimised VHDL code that can be readily deployed on an FPGA. The use of the E-method allows the user great flexibility if targeting high throughput applications.

• Contact: Silviu-Ioan Filip
• Partners: Univ Rennes, Imperial College London
• URL: emethod on github

6.2.3 Firopt: a tool for the simultaneous design of digital FIR filters along with the dedicated hardware model

Participants: Silviu-Ioan Filip, Martin Kumm, Anastasia Volkova.

Keywords: FIR filter design, multiplierless hardware implementation generator

Scientific description: the firopt tool is an open source C++ prototype that produces Finite Impulse Response (FIR) filters that have minimal cost in terms of digital adders needed to implement them. This project aims at fusing the filter design problem from a frequency domain specification with the design of the dedicated hardware architecture. The optimality of the results is ensured by solving appropriate mixed integer linear programming (MILP) models developed for the project. It produces results that are generally more efficient than those of other methods found in the literature or from commercial tools (such as MATLAB).

• Contact: Silviu-Ioan Filip
• Partners: Univ Rennes, Université de Nantes, Fulda University of Applied Sciences
• URL: firopt on gitlab

6.2.4 rminimax: a tool for designing machine-efficient rational approximations of mathematical functions

Participants: Silviu-Ioan Filip.

Keywords: Computer Arithmetic, Function Approximation, Rational and Polynomial Functions, Mathematical Libraries

Scientific description: rminimax is a C++ library for designing $L^{\infty }$-based rational approximations of mathematical function, with both real and machine-representable coefficients (such as IEEE-754 floating-point formats). The output of the tool is intended for use inside custom mathematical function accelerators (both hardware and software-based), for instance in an FPGA context or for mathematical libraries like the libm of the C language.

• Contact: Silviu-Ioan Filip
• Partners: Univ Rennes
• URL: rminimax on gitlab

6.2.5 Hybrid-DBT

Participants: Simon Rokicki, Louis Savary, Steven Derrien.

Keywords: Dynamic Binary Translation, hardware acceleration, VLIW processor, RISC-V

Scientific description: Hybrid-DBT is a hardware/software Dynamic Binary Translation (DBT) framework capable of translating RISC-V binaries into VLIW binaries. Since the DBT overhead has to be as small as possible, our implementation takes advantage of hardware acceleration for performance critical stages (binary translation, dependency analysis and instruction scheduling) of the flow. Thanks to hardware acceleration, our implementation is two orders of magnitude faster than a pure software implementation and enables an overall performance increase of 23% on average, compared to a native RISC-V execution.

• Contact: Simon Rokicki
• Partners: Univ Rennes
• URL: HybridDBT on github

6.2.6 Comet

Participants: Simon Rokicki, Olivier Sentieys, Joseph Paturel.

Keywords: Processor core, RISC-V instruction-set architecture

Scientific description: Comet is a RISC-V pipelined processor with data/instruction caches, fully developed using High-Level Synthesis. The behavior of the core is defined in a small C++ code which is then fed into a HLS tool to generate the RTL representation. Thanks to this design flow, the C++ description can be used as a fast and cycle-accurate simulator, which behaves exactly like the final hardware. Moreover, modifications in the core can be done easily at the C++ level.

• Contact: Simon Rokicki
• Partners: Univ Rennes
• URL: Comet on gitlab

9.1.1 Inria Associate Team

9.1.2 Participation in other International Programs

9.2.1 Visits of international scientists

Hendrik Wohrle, Professor at FH Dortmund, has visited TARAN for three months from Apr. 2023 until June 2023.

Louis Narmour, PhD Student from Colorado State University (CSU), USA, is visiting TARAN from Jan. 2022 for two years, in the context of his international jointly supervised PhD (or ’cotutelle’ in French) between CSU and Univ. Rennes.

Jinyi Xu, PhD Student from East China Normal University, China, has visited TARAN from Nov. 2020 for two years.

Pavitra Bhade, PhD Student from IIT Goa, has visited TARAN for one month in Feb. 2023.

9.2.2 Visits to international teams

Corentin Ferry, PhD student, is visiting Colorado State University (CSU) since Sep. 2021 for two years, in the context of his international jointly supervised PhD (or ’cotutelle’ in French) between CSU and Univ. Rennes.

9.3.1 ANR AdequateDL

Participants: Olivier Sentieys, Silviu-Ioan Filip.

• Program: ANR PRC
• Project acronym: AdequateDL
• Project title: Approximating Deep Learning Accelerators
• Duration: Jan. 2019 - Dec. 2023
• Coordinator: TARAN
• Other partners: INL, LIRMM, CEA-LIST

The design and implementation of convolutional neural networks for deep learning is currently receiving a lot of attention from both industrials and academics. However, the computational workload involved with CNNs is often out of reach for low power embedded devices and is still very costly when run on datacenters. By relaxing the need for fully precise operations, approximate computing substantially improves performance and energy efficiency. Deep learning is very relevant in this context, since playing with the accuracy to reach adequate computations will significantly enhance performance, while keeping quality of results in a user-constrained range. AdequateDL will explore how approximations can improve performance and energy efficiency of hardware accelerators in deep-learning applications. Outcomes include a framework for accuracy exploration and the demonstration of order-of-magnitude gains in performance and energy efficiency of the proposed adequate accelerators with regards to conventional CPU/GPU computing platforms.

9.3.2 ANR RAKES

Participants: Olivier Sentieys, Cédric Killian, Abhijit Das.

• Program: ANR PRC
• Project acronym: RAKES
• Project title: Radio Killed an Electronic Star: speed-up parallel programming with broadcast communications based on hybrid wireless/wired network on chip
• Duration: June 2019 - June 2024
• Coordinator: TIMA
• Other partners: TIMA, TARAN, Lab-STICC

The efficient exploitation by software developers of multi/many-core architectures is tricky, especially when the specificities of the machine are visible to the application software. To limit the dependencies to the architecture, the generally accepted vision of the parallelism assumes a coherent shared memory and a few, either point to point or collective, synchronization primitives. However, because of the difference of speed between the processors and the main memory, fast and small dedicated hardware controlled memories containing copies of parts of the main memory (a.k.a caches) are used. Keeping these distributed copies up-to-date and synchronizing the accesses to shared data, requires to distribute and share information between some if not all the nodes. By nature, radio communications provide broadcast capabilities at negligible latency, they have thus the potential to disseminate information very quickly at the scale of a circuit and thus to be an opening for solving these issues. In the RAKES project, we intend to study how wireless communications can solve the scalability of the abovementioned problems, by using mixed wired/wireless Network on Chip. We plan to study several alternatives and to provide (a) a virtual platform for evaluation of the solutions and (b) an actual implementation of the solutions.

9.3.3 ANR Opticall2

Participants: Olivier Sentieys, Cédric Killian, Daniel Chillet.

• Program: ANR PRCE
• Project acronym: Opticall2
• Project title: on-chip OPTIcal interconnect for ALL to ALL communications
• Duration: Dec. 2018 - May 2024
• Coordinator: INL
• Other partners: INL, TARAN, C2N, CEA-LETI, Kalray

The aim of Opticall2 is to design broadcast-enabled optical communication links in manycore architectures at wavelengths around 1.3um. We aim to fabricate an optical broadcast link for which the optical power is equally shared by all the destinations using design techniques (different diode absorption lengths, trade-off depending on the current point in the circuit and the insertion losses). No optical switches will be used, which will allow the link latency to be minimized and will lead to deterministic communication times, which are both key features for efficient cache coherence protocols. The second main objective of Opticall2 is to propose and design a new broadcast-aware cache coherence communication protocol allowing hundreds of computing clusters and memories to be interconnected, which is well adapted to the broadcast-enabled optical communication links. We expect better performance for the parallel execution of benchmark programs, and lower overall power consumption, specifically that due to invalidation or update messages.

9.3.4 ANR SHNOC

Participants: Cédric Killian, Daniel Chillet, Olivier Sentieys, Emmanuel Casseau, Ibrahim Krayem.

• Program: ANR JCJC (young researcher)
• Project acronym: SHNOC
• Project title: Scalable Hybrid Network-on-Chip
• Duration: Feb. 2019 - Apr. 2024
• P.I.: C. Killian, TARAN

The goal of the SHNoC project is to tackle one of the manycore interconnect issues (scalability in terms of energy consumption and latency provided by the communication medium) by mixing emerging technologies. Technology evolution has allowed for the integration of silicon photonics and wireless on-chip communications, creating Optical and Wireless NoCs (ONoCs and WNoCs, respectively) paradigms. The recent publications highlight advantages and drawbacks for each technology: WNoCs are efficient for broadcast, ONoCs have low latency and high integrated density (throughput/sqcm) but are inefficient in multicast, while ENoCs are still the most efficient solution for small/average NoC size. The first contribution of this project is to propose a fast exploration methodology based on analytical models of the hybrid NoC instead of using time consuming manycore simulators. This will allow exploration to determine the number of antennas for the WNoC, the amount of embedded lasers sources for the ONoC and the routers architecture for the ENoC. The second main contribution is to provide quality of service of communication by determining, at run-time, the best path among the three NoCs with respect to a target, e.g. minimizing the latency or energy. We expect to demonstrate that the three technologies are more efficient when jointly used and combined, with respect to traffic characteristics between cores and quality of service targeted.

9.3.5 ANR FASY

Participants: Angeliki Kritikakou, Marcello Traiola, Olivier Sentieys.

• Program: ANR JCJC (young researcher)
• Project acronym: FASY
• Project title: FAult-aware timing behaviour for safety-critical multicore SYstems
• Duration: Jan. 2022 - Dec. 2025
• P.I.: K. Kritikakou, TARAN

The safety-critical embedded industries, such as avionics, automobile, robotics and health-care, require guarantees for hard real-time, correct application execution, and architectures with multiple processing elements. While multicore architectures can meet the demands of best-effort systems, the same cannot be stated for critical systems, due to hard-to-predict timing behaviour and susceptibility to reliability threats. Existing approaches design systems to deal with the impact of faults regarding functional behaviors. FASY extends the SoA by answering the two-fold challenge of time-predictable and reliable multicore systems through functional and timing analysis of applications behaviour, fault-aware WCET estimation and design of cores with time-predictable execution, under faults.

9.3.6 ANR Re-Trusting

Participants: Olivier Sentieys, Angeliki Kritikakou, Marcello Traiola, Silviu-Ioan Filip.

• Program: ANR PRC
• Project acronym: Re-Trusting
• Project title: REliable hardware for TRUSTworthy artificial INtelliGence
• Duration: Oct. 2021 - Sep. 2025
• Coordinator: INL
• Other partners: LIP6, TARAN, THALES

To be able to run Artificial Intelligence (AI) algorithms efficiently, customized hardware platforms for AI (HW-AI) are required. Reliability of hardware becomes mandatory for achieving trustworthy AI in safety-critical and mission-critical applications, such as robotics, smart healthcare, and autonomous driving. The RE-TRUSTING project develops fault models and performs failure analysis of HW-AIs to study their vulnerability with the goal of “explaining” HW-AI. Explaining HW-AI means ensuring that the hardware is error-free and that the AI hardware does not compromise the AI prediction accuracy and does not bias AI decision-making. In this regard, the project aims at providing confidence and trust in decision-making based on AI by explaining the hardware wherein AI algorithms are being executed.

9.3.7 Labex CominLabs - LeanAI (2021-2024)

Participants: Silviu-Ioan Filip (PI), Olivier Sentieys, Steven Derrien.

Recent developments in deep learning (DL) are putting a lot of pressure on and pushing the demand for intelligent edge devices capable of on-site learning. The realization of such systems is, however, a massive challenge due to the limited resources available in an embedded context and the massive training costs for state-of-the-art deep neural networks. In order to realize the full potential of deep learning, it is imperative to improve existing network training methodologies and the hardware being used. LeanAI will attack these problems at the arithmetic and algorithmic levels and explore the design of new mixed numerical precision hardware architectures that are at the same time more energy-efficient and offer increased performance in a resource-restricted environment. The expected outcome of the project includes new mixed-precision algorithms for neural network training, together with open-source tools for hardware and software training acceleration at the arithmetic level on edge devices. Partners: TARAN, LS2N/OGRE, INRIA-LIP/DANTE.

9.3.8 ANR LOTR

Participants: Steven Derrien, Simon Rokicki.

• Program: ANR PRC
• Project acronym: LOTR
• Project title: Lord Of The RISCs
• Duration: Oct. 2023 - Sep. 2027
• Coordinator: Steven Derrien
• Other partners: CEA, TARAN, PACAP

Lord Of The RISCs (LOTR) is a novel flow for designing highly customized RISC-V processor microarchitectures for embedded and IoT platforms. The LOTR flow operates on a description of the processor Instruction Set Architecture (ISA). It can automatically infer synthesizable Register Transfer Level (RTL) descriptions of a large number of microarchitecture variants with different performance/cost trade-offs. In addition, the flow integrates two domain-specific toolboxes dedicated to the support of timing predictability (for safety-critical systems) and security (through hardware protection mechanisms).

9.3.9 CYBERPROS

Participants: Olivier Sentieys.

• Program: BPI France
• Project title: Fault Injection Emulator for Cyberattacks and System Security Evaluation processeurs
• Duration: Oct. 2023 - Sep. 2026
• Coordinator: Patrice Deroux-Dauphin
• Other partners: TEMENTO, IROC

The objective of the CYBERPROS project is to be able to predict the behavior of a circuit subjected to to cyberattacks by fault injection. The research work consists of developing a active attack emulator and associated simulation tools. A hardened processor core will be developed as a test vehicle. Test results will be digitized for editing of learning algorithms underlying the creation of a database and tools for predictive behavior.

9.3.10 PEPR ARSENE

Participants: Louis Savary, Herinomena Andrianatrehina, Simon Rokicki, Steven Derrien, Ronan Lashermes, Olivier Sentieys.

• Program: PEPR Cyber
• Project title: Secure architectures for embedded digital systems
• Duration: Jul. 2022 - Jun. 2028
• Coordinator: CEA
• Other partners: CEA, PACAP, TARAN, LHC, Lab-STICC, LIRMM, Verimag, TIMA, LCIS, EMSE, Telecom Paris

The main objectives of the ARSENE project are to allow the French community to make significant advances in the field to strengthen the community’s expertise and visibility on the international stage. Taran's contribution is on the study and implementation of two families of RISC-V processors: 32-bit RISC-V for low power secure circuits against physical attacks for IoT applications and 64-bit RISC-V secure circuits against micro-architectural attacks.

9.3.11 ANR RADYAL

Participants: Marcello Traiola, Olivier Sentieys.

• Program: ANR PRC
• Project acronym: RADYAL
• Project title: Resource-Aware DYnamically Adaptable machine Learning
• Duration: Oct 2023 – Apr 2027
• Coordinator: Stefan Duffner, LIRIS, Lyon
• Other partners: TARAN, LIRIS, CTRL-A (Inria Grenoble), GIPSA-LAB

Nowadays, for many applications, the performance requirements of a DNN model deployed on a given hardware platform are not static but evolving dynamically as its operating conditions and environment change. RADYAL studies original interdisciplinary approaches that allow DNN models to be dynamically configurable at run-time on a given reconfigurable hardware accelerator architecture, depending on the external environment, following an approach based on feedback loops and control theory.

9.3.12 ANR SEC-V

Participants: Bertrand LE GAL.

• Program: ANR PRCE
• Project acronym: SEC-V
• Project title: open-source, secure and high-performance processor core based on the RISC-V ISA
• Duration: Oct 2021 – Apr 2025
• Coordinator: Sebastien Pillement, IETR, Nantes
• Other partners: TARAN, LS2N, THALES TRT, THALES INVIA

In recent years, attacks exploiting optimization mechanisms have appeared. Exploiting, for example, flaws in cache memories, performance counters or speculation units, they call into question the safety and security of processors and the industrial systems that use them. SEC-V studies original interdisciplinary approaches that rely on RISC-V open-hardware architectures and CISC paradigm to prodive runtime flexibility and adaptability. The originality of the approach lies in the integration of a dynamic code transformation unit covering 4 of the 5 NIST functions of cybersecurity, notably via monitoring (identify, detect), obfuscation (protect), and dynamic adaptation (react). This dynamic management paves the way for on-line optimizations to improve the security and safety of the microarchitecture, without reworking either the software or the chip architecture.

10.1.1 Scientific events: organisation

10.1.2 Scientific events: selection

10.1.3 Member of the editorial boards of Journals

• D. Chillet is member of the Editor Board of Journal of Real-Time Image Processing (JRTIP).
• A. Kritikakou is Handling Editor for Elsevier Microprocessors and Microsystems Journal.
• A. Kritikaou is Associate editor in Elsevier Journal of Systems Architecture.
• O. Sentieys is member of the editorial board of Journal of Low Power Electronics.

10.1.4 Invited talks

• M. Traiola was an invited speaker at FETCH 2023.
• M. Traiola was an invited panelist at the 8th Workshop on Approximate Computing (AxC23) @ IEEE/IFIP DSN 2023.
• A. Kritikakou gave an invited talk on ”Reliability analysis and protection of RISC-V processors for safety-critical embedded systems” at BITFLIP workshop during the European Cyber Week (ECW) 2023.
• A. Kritikakou gave an invited talk on ”Reliability analysis and protection for AI critical embedded systems” at BarCamp x-GDR 2023 on implementation challenges of AI.
• O. Sentieys gave an invited talk at the European Nanoelectronics Applications Design and Technology Conference (ADTC) on ”Design and Exploration of RISC-V Cores from High-Level Specifications”.
• O. Sentieys gave an invited presentation at the Inria Scientific Days on ”Computing beyond Moore's Law”.
• S. Derrien gave an invited presentation at the Inria Scientific Days on ”How to (not) blow-up a pipeline”.

10.1.5 Leadership within the scientific community

• D. Chillet is a member of the French National University Council in Signal Processing and Electronics (CNU - Conseil National des Universites, 61ème section) since 2019.
• D. Chillet is member of the Board of Directors of Gretsi Association.
• D. Chillet is co-animator of the "Connected Objects" topic of GDR SoC2.
• A. Kritikakou is a member of the French National University Council in Computer Science (CNU - Conseil National des Universites, 27ème section) since 2022.
• A. Kritikakou is co-animator of the "High performance embedded computing" topic of GDR SoC2.
• F. Charot and O. Sentieys are members of the steering committee of a CNRS Spring School for graduate students on embedded systems architectures and associated design tools (ARCHI).
• O. Sentieys is a member of the steering committee of GDR SoC2.
• O. Sentieys is an elected member of the Evaluation Committee (CE) of Inria.

10.1.6 Scientific expertise

• D. Chillet was a member of the HCERES Evaluation Committee for Master Programs of Université Nice Côte d'Azur.
• O. Sentieys was a member of the ANR Scientific Evaluation Committee CE25 "Software science and engineering - Multi-purpose communication networks, high-performance infrastructure".

10.1.7 Research administration

• S. Derrien is the head of the D3 "Computer Architecture" Department of IRISA Lab.

10.1.8 Standardization activities

• S. Filip and O. Sentieys are members of the IEEE P3109 Standardization Group on Arithmetic Formats for Machine Learning.

10.2.1 Teaching administration

• D. Chillet is associate director of studies at ENSSAT Engineering Graduate School.
• E. Casseau is in charge of the Department of “Digital Systems” at ENSSAT Engineering Graduate School.
• D. Chillet is the responsible of the ”Embedded Systems” major of the SISEA Master by Research.
• S. Rokicki is the responsible of the second year in the computer science department of ENS Rennes

10.2.2 Teaching

• E. Casseau: programmable logic, 30h, Enssat (L3)
• E. Casseau: low power design, 8h, Enssat (M1)
• E. Casseau: real time design methodology, 54h, Enssat (M1)
• E. Casseau: computer architecture, 24h, Enssat (M1)
• E. Casseau: VHDL design, 42h, Enssat (M1)
• E. Casseau: SoC and high-level synthesis, 24h, Enssat (M2)
• D. Chillet: embedded processor architecture, 20h, Enssat (M1)
• D. Chillet: multimedia processor architectures, 30h, Enssat (M2)
• D. Chillet: advanced processor architectures, 20h, Enssat (M2)
• D. Chillet: advanced processor architectures, 15h, Embedded Systems Master (M2)
• D. Chillet: micro-controller, 32h, Enssat (L3)
• D. Chillet: low-power digital CMOS circuits, 4h, UBO (M2)
• D. Chillet: Processor architectures, 40h, USTH (B2)
• S. Derrien, optimizing and parallelising compilers, 14h, Master of Computer Science, istic (M2)
• S. Derrien, advanced processor architectures, 8h, Master of Computer Science, istic (M2)
• S. Derrien, high level synthesis, 20h, Master of Computer Science, istic (M2)
• S. Derrien: introduction to operating systems, 8h, istic (M1)
• S. Derrien, principles of digital design, 20h, Bachelor of EE/CS, istic (L2)
• S. Derrien, computer architecture, 48h, Bachelor of Computer Science, istic (L3)
• S. Filip: Operating Systems, 24h, ENS Rennes (Aggregation Informatique)
• A. Kritikakou: Tools and programming in C, 24.75h, istic (L3)
• A. Kritikakou: Computer programming, 22.5h, istic (L3)
• A. Kritikakou: Unix commands and programming, 6.75h, istic (L3)
• A. Kritikakou: Fault tolerant embedded systems, 6h, INSA (M2)
• A. Kritikakou: Energy sobriety of digital architectures, 7.5h, INSA (M2)
• S. Rokicki: C Programming, 24h, ENS Rennes
• O. Sentieys: VLSI integrated circuit design, 24h, Enssat (M1)
• O. Sentieys: VHDL and logic synthesis, 18h, Enssat (M1)
• O. Sentieys: Hardware Accelerators for Deep Neural Networks, 54h, Master of Embedded Systems, istic (M2)
• M. Traiola: Operating Systems, 24h, ENS Rennes (Aggregation Mecatronique)

10.2.3 PhD Supervision

• PhD: Thibault Allenet, Quantization and adversarial robustness of embedded deep neural networks, March 2023, O. Sentieys, O. Bichler (CEA LIST) 53.
• PhD: Minh Thanh Cong, Hardware accelerated simulation and automatic design of heterogeneous architecture, March 2023, F. Charot, S. Derrien 54.
• PhD: Van-Phu Ha, Contributions to the scalability of automatic precision tuning, March 2023, O. Sentieys 55.
• PhD in progress: Hamza Amara, Detection and countermeasures for DoS attack in Noc-based SoC using machine learning, Oct. 2022, E. Casseau, D. Chillet, C. Killian.
• PhD in progress: Herinomena Andrianatrehina, Ensuring confidentiality in modern Out-of-Order cores, Nov 2022, S. Rokicki, R. Lashermes.
• PhD in progress: Gaetan Barret, Predictive model of energy consumption of cloud-native applications, Nov. 2022, D. Chillet.
• PhD in progress: Sami Ben Ali, Efficient Low-Precision Training for Deep Learning Accelerators, Jan. 2022, O. Sentieys, S. Filip.
• PhD in progress: Benoit Coqueret, Physical Security Attacks Against Artificial Intelligence Based Algorithms, CIFRE Thesis with Thales, Nov. 2022, O. Sentieys, M. Carbone (Thales), G. Zaid (Thales).
• PhD in progress: Léo De La Fuente, In-Memory Computing for Ultra Low Power Architectures, Nov. 2021, O. Sentieys, J.-F. Christmann (CEA).
• PhD in progress: Paul Estano, Dynamic Precision Training of Deep Neural Network Models on the Edge, Feb. 2022, S. Filip, E. Riccietti (ENS Lyon), S. Derrien.
• PhD in progress: Corentin Ferry, Compiler support for Runtime data compression for FPGA accelerators, Sep. 2019, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Univ Rennes and Colorado State University).
• PhD in progress: Cédric Gernigon, Highly compressed/quantized neural networks for FPGA on-board processing in Earth observation by satellite, Oct. 2020, O. Sentieys, S. Filip.
• PhD in progress: Jean-Michel Gorius, Speculative Software Pipeline for Micro-Architecture Synthesis, Oct. 2021, S. Derrien, S. Rokicki.
• PhD in progress: Wilfread Guilleme, Fault Tolerant Hardware Architectures for Artificial Intelligence, Oct. 2022, D. Chillet, C. Killian, A.Kritikakou.
• PhD in progress: Ibrahim Krayem, Fault tolerant emerging on-chip interconnects for manycore architectures, Oct. 2020, C. Killian, D. Chillet.
• PhD in progress: Seungah Lee, Efficient Designs of On-Board Heterogeneous Embedded Systems for Space Applications, Nov. 2021, A. Kritikakou, E. Casseau, R. Salvador, O. Sentieys.
• PhD in progress: Dylan Leothaud, Automatic synthesis of secure and predictable processors for the Internet of Thing, Oct. 2023, S. Derrien, S. Rokicki.
• PhD in progress: Guillaume Lomet, Guess What I'm Learning: Side-Channel Analysis of Edge AI Training Accelerators, Oct. 2022, C. Killian, R. Salvador, O. Sentieys
• PhD in progress: Amélie Marotta, Emp-error: EMFI-Resilient RISC-V Processor, Oct. 2021, O. Sentieys, R. Lashermes (LHS), Rachid Dafali (DGA).
• PhD in progress: Louis Narmour, Revisiting memory allocation in the polyhedral model, Sep. 2019, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Université de Rennes 1 and Colorado State University).
• PhD in progrees: Romaric (Pegdwende) Nikiema, Time-guaranteed and reliable execution for real-time multicore architectures, Oct. 2022, A. Kritikakou, M. Traiola
• PhD in progress: Leo Pajot, Soft-core processor with dynamic binary execution exploiting instruction-level parallelism, CIFRE Thesis with KEYSOM SAS, Sep. 2023, B. Le Gal.
• PhD in progress: Leo Pradels, Constrained optimization of FPGA accelerators for embedded deep convolutional neural networks, CIFRE Thesis with Safran, Dec. 2020, D. Chillet, O. Sentieys, S. Filip.
• PhD in progress: Baptiste Rossigneux, Adapting sparsity to hardware in neural networks, Nov. 2022, E. Casseau, I. Kucher (CEA), V. Lorrain (CEA).
• PhD in progress: Louis Savary, Security of DBT-based processors, Sept 2022, S. Rokicki, S. Derrien.

10.3.1 Interventions

As part of a collaboration between multiple institutes and universities (Inria Rennes, the Federal University of Rio Grande do Sul, and the University of Trento), we helped develop a demonstration showcasing radiation-induced faults' impacts on Deep Neural Networks (DNNs) at the ChipIr Facility in the Rutherford Appleton Laboratory, located in Didcot, UK. The demonstration consists of an NVIDIA Jetson Orin board running a DNN and performing semantic segmentation on a self-driving car video of London. A large red button is placed to simulate a radiation-induced fault occurring during the DNN execution. Users can see in real-time how an unprotected DNN could affect the reliability of an autonomous car by just pushing the red button. This platform is used for demonstrations to high school and college students from the Oxford region while visiting the facility.

International journals

• 12 articleM.Minyu Cui, A.Angeliki Kritikakou, L.Lei Mo and E.Emmanuel Casseau. Near-Optimal Energy-Efficient Partial-Duplication Task Mapping of Real-Time Parallel Applications.Journal of Systems Architecture134January 2023, 102790HALDOIback to text
• 13 articleP.Petr Dobiáš, E.Emmanuel Casseau and O.Oliver Sinnen. Online Fault Tolerant Energy-Aware Algorithm for CubeSats.Sustainable Computing : Informatics and SystemsMarch 2023, 100853HALDOI
• 14 articleF.Fernando Fernandes dos Santos, L.Luigi Carro, F.Flavio Vella and P.Paolo Rech. Assessing the Impact of Compiler Optimizations on GPUs Reliability.ACM Transactions on Architecture and Code OptimizationJanuary 2024HALDOI
• 15 articleC.Corentin Ferry, T.Tomofumi Yuki, S.Steven Derrien and S.Sanjay Rajopadhye. Increasing FPGA Accelerators Memory Bandwidth with a Burst-Friendly Memory Layout.IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems2023, 1-15HALDOIback to text
• 16 articleC.Clémence Gillet, A.Adrien Vincent, B.Bertrand Le Gal and S.Sylvain Saïghi. A High-Level Methodology to Evaluate and Optimize Digital Architectures Targeting Spike Encoding.IEEE Access112023, 120654-120665HALDOI
• 17 articleP.Prachi Kashikar, O.Olivier Sentieys and S.Sharad Sinha. Lossless Neural Network Model Compression Through Exponent Sharing.IEEE Transactions on Very Large Scale Integration (VLSI) Systems31November 2023, 1816 - 1825HALDOIback to text
• 18 articleI.Ibrahim Krayem, J. O.Joel Ortiz Sosa, C.Cédric Killian and D.Daniel Chillet. Analytical Model for Performance Evaluation of Token-Passing-Based WiNoCs.IEEE Design & Test406August 2023, 136-148HALDOIback to text
• 19 articleA.Angeliki Kritikakou and S.Stefanos Skalistis. Mitigating Mode-Switch through Run-time Computation of Response Time.ACM Transactions on Design Automation of Electronic Systems285September 2023, 1-26HALDOIback to text
• 20 articleB.Bertrand Le Gal, C.Christophe Jego and V.Vincent Pignoly. High-performance hard-input LDPC decoding on multi-core devices for optical space links.Journal of Systems Architecture137April 2023, 102832HALDOI
• 21 articleL.Lei Mo, X.Xinmei Li, A.Angeliki Kritikakou and P.Pengcheng You. Optimal IC Task Mapping to Maximize QoS on Heterogeneous Multicore Systems.IEEE Transactions on Circuits and Systems II: Express BriefsNovember 2023, 1-5HALDOIback to text
• 22 articleL.Lei Mo, Q.Qi Zhou, A.Angeliki Kritikakou and X.Xianghui Cao. Energy Optimized Task Mapping for Reliable and Real-Time Networked Systems.ACM Transactions on Sensor NetworksFebruary 2023, 1-24HALDOIback to text
• 23 articleC.Camille Monière, B.Bertrand Le Gal and E.Emmanuel Boutillon. Real-time energy-efficient software and hardware implementations of a QCSP communication system.Journal of Systems Architecture141August 2023, 102933HALDOI
• 24 articleA.Annachiara Ruospo, E.Ernesto Sanchez, L.Lucas Matana Luza, L.Luigi Dilillo, M.Marcello Traiola and A.Alberto Bosio. A Survey on Deep Learning Resilience Assessment Methodologies.Computer56February 2023, 57-66HALDOIback to text

International peer-reviewed conferences

• 25 inproceedingsS.Sami Ben Ali, S.-I.Silviu-Ioan Filip and O.Olivier Sentieys. A Stochastic Rounding-Enabled Low-Precision Floating-Point MAC for DNN Training.27th IEEE/ACM Design, Automation and Test in Europe (DATE)Valencia, SpainMarch 2024, 1-6HALback to text
• 26 inproceedingsA.Alberto Bosio, S.Samuele Germiniani, G.Graziano Pravadelli and M.Marcello Traiola. Exploiting assertions mining and fault analysis to guide RTL-level approximation.DATE 2023 – 26th IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumApril 2023HALback to text
• 27 inproceedingsBest paperN.Nicolas Brisebarre and S.-I.Silviu-Ioan Filip. Towards Machine-Efficient Rational L ∞ -Approximations of Mathematical Functions.Proceedings of the 30th IEEE International Symposium on Computer Arithmetic ARITH 2023, Sep 2023, Portland, Oregon, USA30th IEEE International Symposium on Computer Arithmetic ARITH 2023Portland, United StatesSeptember 2023HALback to textback to text
• 28 inproceedingsB.Benoît Coqueret, M.Mathieu Carbone, O.Olivier Sentieys and G.Gabriel Zaid. When Side-Channel Attacks Break the Black-Box Property of Embedded Artificial Intelligence.AISec 2023 - 16th ACM Workshop on Artificial Intelligence and SecurityCopenhagen, DenmarkACMNovember 2023, 127-138HALDOIback to text
• 29 inproceedingsF.Fernando Fernandes dos Santos, L.Luigi Carro and P.Paolo Rech. Understanding and Improving GPUs' Reliability Combining Beam Experiments with Fault Simulation.ITC 2023 - IEEE International Test ConferenceAnaheim, United StatesIEEE2023, 176-185HALDOI
• 30 inproceedingsC.Cédric Gernigon, S.-I.Silviu-Ioan Filip, O.Olivier Sentieys, C.Clément Coggiola and M.Mickael Bruno. Low-Precision Floating-Point for Efficient On-Board Deep Neural Network Processing.European Data Handling & Data Processing Conference (EDHPC)Juan-Les-Pins, FranceOctober 2023, 1-8HALback to text
• 31 inproceedingsJ.-M.Jean-Michel Gorius, S.Simon Rokicki and S.Steven Derrien. A Unified Memory Dependency Framework for Speculative High-Level Synthesis.CC'24 - ACM SIGPLAN 2024 International Conference on Compiler ConstructionEdinburgh (Ecosse), United KingdomMarch 2024HALback to text
• 32 inproceedingsW.Wilfread Guilleme, Y.Youri Helen, R.Rémy Priem, A.Angeliki Kritikakou, D.Daniel Chillet and C.Cédric Killian. Protection sélective d’un réseau de neurones implémenté sur puce FPGA soumis à un environnement radiatif.Gretsi 2023 - XXIXème Colloque Francophone de Traitement du Signal et des ImagesGrenoble, France2023, 1-4HALback to text
• 33 inproceedingsV.-P.Van-Phu Ha and O.Olivier Sentieys. Maximizing Computing Accuracy on Resource-Constrained Architectures.DATE 2023 - 26th IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumIEEEApril 2023, 1-6HALback to text
• 34 inproceedingsS. S.Sara Sadat Hoseininasab, C.Caroline Collange and S.Steven Derrien. Rapid Prototyping of Complex Micro-architectures Through High-Level Synthesis.Applied Reconfigurable ComputingARC 2023 - 19th International Symposium on Applied Reconfigurable Computing14251Lecture Notes in Computer ScienceCottbus, GermanySpringer Nature Switzerland2023, 19 - 34HALDOIback to text
• 35 inproceedingsI.Ibrahim Krayem, J. O.Joel Ortiz Sosa, C.Cédric Killian and D.Daniel Chillet. Analytical Model for Performance Evaluation of Token-Passing Based WiNoCs.NOCS 2023 - 17th IEEE/ACM International Symposium on Networks‑on‑ChipHamburg, Germany2023HALback to text
• 36 inproceedingsS.Seungah Lee, R.Ruben Salvador, A.Angeliki Kritikakou, O.Olivier Sentieys, J.Julien Galizzi and E.Emmanuel Casseau. High-Level Synthesis-Based On-board Payload Data Processing considering the Roofline Model.EDHPC 2023 proceedingsEDHPC 2023 - European Data Handling & Data Processing ConferenceJuan-Les-Pins, FranceOctober 2023, 1-10HALback to text
• 37 inproceedingsM.Matthieu Magnant, M. A.Mohamed Amine Ben Temim, B.Bertrand Le Gal, G.Guillaume Ferré and F.Florian Collard. Implantation d'un détecteur de préambules vobulés par satellite en orbite basse.Gretsi 2023 - XXIXème Colloque Francophone de Traitement du Signal et des ImagesGrenoble, France2023, 1-4HAL
• 38 inproceedingsL.Louis Narmour, S.Steven Derrien and S.Sanjay Rajopadhye. Automatic Algorithm-Based Fault Tolerance (AABFT) of Stencil Computations.PACT '23: Proceedings of the International Conference on Parallel Architectures and Compilation TechniquesPACT 2023 - International Conference on Parallel Architectures and Compilation TechniquesVienna, Austria2023, 1-12HALback to text
• 39 inproceedingsP. R.Pegdwende Romaric Nikiema, A.Angeliki Kritikakou, M.Marcello Traiola and O.Olivier Sentieys. Impact of Transient Faults on Timing Behavior and Mitigation with Near-Zero WCET Overhead.ECRTS 2023 - 35th Euromicro Conference on Real-Time SystemsVienna, AustriaSchloss Dagstuhl – Leibniz-Zentrum für Informatik2023, 1-22HALDOIback to text
• 40 inproceedingsP. R.Pegdwende Romaric Nikiema, A.Angeliki Kritikakou, M.Marcello Traiola, O.Olivier Sentieys and O.Olivier Sentieys. Design with low complexity fine-grained Dual Core Lock-Step (DCLS) RISC-V processors.DSN 2023 - 53rd Annual IEEE/IFIP International Conference on Dependable Systems and NetworksPorto, PortugalIEEE2023, 224-229HALDOIback to text
• 41 inproceedingsP. R.Pegdwende Romaric Nikiema, A.Alessandro Palumbo, A.Allan Aasma, L.Luca Cassano, A.Angeliki Kritikakou, A.Ari Kulmala, J.Jari Lukkarila, M.Marco Ottavi, R.Rafail Psiakis and M.Marcello Traiola. Towards Dependable RISC-V Cores for Edge Computing Devices.IOLTS 2023 - IEEE 29th International Symposium on On-Line Testing and Robust System DesignCrete, GreeceIEEE2023, 1-7HALDOIback to text
• 42 inproceedingsJ.Joseph Paturel, C.Clément Quinson, M.Martin Quinson and S.Simon Rokicki. SmolPhone: a smartphone with energy limits.IGSC 2023 - 14th International Green and Sustainable ComputingToronto, CanadaOctober 2023, 4HAL
• 43 inproceedingsA.Ali Piri, S.Salvatore Pappalardo, S.Salvatore Barone, M.Mario Barbareschi, B.Bastien Deveautour, M.Marcello Traiola, I.Ian O’connor and A.Alberto Bosio. Input-aware accuracy characterization for approximate circuits.DSN-W 2023 - 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks WorkshopsPorto, PortugalIEEE2023, 179-182HALDOIback to text
• 44 inproceedingsB.Baptiste Rossigneux, I.Inna Kucher, V.Vincent Lorrain and E.Emmanuel Casseau. Surround the Nonlinearity: Inserting Foldable Convolutional Autoencoders to Reduce Activation Footprint.proceedings of 2023 IEEE/CVF International Conference on Computer Vision WorkshopsICCVW 2023 - IEEE/CVF International Conference on Computer Vision WorkshopsParis, FranceIEEE2023, 1399-1403HALDOIback to text
• 45 inproceedingsM.Marcello Traiola, A.Angeliki Kritikakou and O.Olivier Sentieys. A machine-learning-guided framework for fault-tolerant DNNs.DATE 2023 – 26th IEEE/ACM Design, Automation and Test in EuropeAntwerp, BelgiumApril 2023, 1-2HALback to text
• 46 inproceedingsM.Marcello Traiola, A.Angeliki Kritikakou and O.Olivier Sentieys. harDNNing: a machine-learning-based framework for fault tolerance assessment and protection of DNNs.ETS 2023 - IEEE European Test SymposiumVenise, ItalyIEEEMay 2023, 1-6HALback to text

Conferences without proceedings

• 47 inproceedingsF.Fernando Fernandes dos Santos, A.Angeliki Kritikakou and O.Olivier Sentieys. Reliability evaluation of Convolutional Neural Network's basic operations on a RISC-V processor.NSREC 2023 - IEEE Nuclear & Space Radiation Effects ConferenceKansas City, MO, United StatesIEEEJuly 2023, 1-6HALback to text
• 48 inproceedingsF.Fernando Fernandes dos Santos, P.Paolo Rech, A.Angeliki Kritikakou and O.Olivier Sentieys. Neutron-Induced Error Rate of Vision Transformer Models on GPUs.RADECS - RADiation and its Effects on Components and Systems ConferenceToulouse, FranceSeptember 2023HALback to text
• 49 inproceedingsJ.-D.Juan-David Guerrero-Balaguera, J. E.Josie E. Rodriguez Condia, F. F.Fernando F. dos Santos, M.Matteo Sonza and P.Paolo Rech. Understanding the Effects of Permanent Faults in GPU's Parallelism Management and Control Units.SC 2023 - ACM/IEEE International Conference for High Performance Computing, Networking, Storage, and AnalysisDenver, United StatesIEEENovember 2023, 1-12HAL
• 50 inproceedingsM.Michel Lemaire, D.Daniel Massicotte, J.Jeremy Poupart, P.Patrice Quinton and S.Sanjay Rajopadhye. Polyhedra at Work: Automatic Generation of VHDL Code for the Sherman-Morrison Formula.Impact24Munich, GermanyJanuary 2024HALback to text
• 51 inproceedingsM.Marcello Traiola, F.Fernando Fernandes Dos Santos, O.Olivier Sentieys and A.Angeliki Kritikakou. Impact of High-Level-Synthesis on Reliability of Neural Network Hardware Accelerators.NSREC 2023 - IEEE Nuclear & Space Radiation Effects ConferenceKansas City (US), United StatesJuly 2023, 1-5HALback to text

Scientific book chapters

• 52 inbookM.Mario Barbareschi, S.Salvatore Barone, A.Alberto Bosio and M.Marcello Traiola. Automatic Approximation of Computer Systems Through Multi-objective Optimization.Design and Applications of Emerging Computer SystemsSpringer Nature SwitzerlandAugust 2024, 383-420HALDOIback to text

Doctoral dissertations and habilitation theses

• 53 thesisT.Thibault Allenet. Quantization and adversarial robustness of embedded deep neural networks.Université de RennesMarch 2023HALback to textback to text
• 54 thesisM. T.Minh Thanh Cong. Hardware accelerated simulation and automatic design of heterogeneous architecture.Université de RennesMarch 2023HALback to text
• 55 thesisV.-P.Van-Phu Ha. Contributions to the scalability of automatic precision tuning.Université de RennesMarch 2023HALback to text