Bibliography

Major publications by the team in recent years

1C. André.

Syntax and Semantics of the Clock Constraint Specification Language (CCSL), Inria, 05 2009, 37 p, RR-6925.

http://hal.inria.fr/inria-00384077/en/
2C. André, J. Deantoni, F. Mallet, R. de Simone.

The Time Model of Logical Clocks available in the OMG MARTE profile, in: Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, S. K. Shukla, J.-P. Talpin (editors), Springer Science+Business Media, LLC 2010, Jul 2010, p. 201–227, Chapter 7.

http://hal.inria.fr/inria-00495664
3C. André, F. Mallet, R. de Simone.

Modeling Time(s), in: MoDELS'2007 10th Intern. Conf. on Model Driven Engineering Languages and Systems, 2007.
4A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.

Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE, January 2003.
5J. Boucaron, A. Coadou, R. de Simone.

Formal Modeling of Embedded Systems with Explicit Schedules and Routes, in: Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, S. K. Shukla, J.-P. Talpin (editors), Springer Science+Business Media, LLC 2010, Jul 2010, p. 41–78, Chapter 2.

http://hal.inria.fr/inria-00495667
6J. Boucaron, R. de Simone, J.-V. Millo.

Latency-insensitive design and central repetitive scheduling, in: MEMOCODE, 2006, p. 175-183.

http://dx.doi.org/10.1109/MEMCOD.2006.1695923
7L. Cucu, N. Pernet, Y. Sorel.

Periodic real-time scheduling: from deadline-based model to latency-based model, in: Annals of Operations Research, 2007.

http://www-rocq.inria.fr/syndex/publications/pubs/aor07/aor07.pdf
8T. Grandpierre, C. Lavarenne, Y. Sorel.

Optimized Rapid Prototyping For Real-Time Embedded Heterogeneous multiprocessors, in: Proceedings of 7th International Workshop on Hardware/Software Co-Design, CODES'99, 1999.
9T. Grandpierre, Y. Sorel.

From Algorithm and Architecture Specification to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations, in: Proceedings of First ACM and IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE'03, Mont Saint-Michel, France, June 2003.

http://www-rocq.inria.fr/syndex/publications/pubs/memocode03/memocode03.pdf
10P. Meumeu Yomsi, Y. Sorel.

Extending Rate Monotonic Analysis with Exact Cost of Preemptions for Hard Real-Time Systems, in: Proceedings of 19th Euromicro Conference on Real-Time Systems, ECRTS'07, Pisa, Italy, July 2007.

http://www-rocq.inria.fr/syndex/publications/pubs/ecrts07/ecrts07.pdf
11D. Potop-Butucaru, Benoît. Caillaud.

Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications, in: Fundam. Inf., January 2007, vol. 78, p. 131–159.

http://portal.acm.org/citation.cfm?id=1366007.1366013
12D. Potop-Butucaru, R. de Simone, Y. Sorel.

From Synchronous Specifications to Statically-Scheduled Hard Real-Time Implementations, in: Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, S. K. Shukla, J.-P. Talpin (editors), Springer Science+Business Media, LLC 2010, Jul 2010, p. 229–262, Chapter 8.

http://hal.inria.fr/inria-00495666
13D. Potop-Butucaru, S. Edwards, G. Berry.

Compiling Esterel, Springer, 2007.
14D. Potop-Butucaru, R. de Simone.

Optimizations for Faster Execution of Esterel Programs, in: MEMOCODE'03, 2003.
15R. de Simone, D. Potop-Butucaru, Jean-Pierre. Talpin.

The Synchronous Hypothesis and Synchronous Languages, in: Embedded Systems Handbook, CRC Press, 2005, chap. 8.

Publications of the year

Doctoral Dissertations and Habilitation Theses

16J.-F. Le Tallec.

Extraction de modèles pour la conception de systèmes sur puce, Université de Nice Sophia Antipolis, January 2012.
17M. Marouf.

Ordonnancement temps réel dur multiprocesseur tolérant aux fautes appliqué à la robotique mobile, Ecole des Mines de Paris, Spécialité Informatique temps réel, robotique et automatique, 2012.

http://www-rocq.inria.fr/syndex/publications/pubs/theses/THMM.pdf

Articles in International Peer-Reviewed Journals

18M. Bachir, S. Touati, F. Brault, D. Gregg, A. Cohen.

Minimal Unroll Factor for Code Generation of Software Pipelining, in: International Journal of Parallel Programming, 2012, p. 1-58.

http://dx.doi.org/10.1007/s10766-012-0203-z
19C. Glitia, J. Deantoni, F. Mallet, J.-V. Millo, P. Boulet, A. Gamatié.

Progressive and explicit refinement of scheduling for multidimensional data-flow applications using uml marte, in: Design Automation for Embedded Systems, 2012, vol. 16, n^o 2, p. 137-169. [ DOI : 10.1007/s10617-012-9093-y ]

http://hal.inria.fr/hal-00727239
20J.-V. Millo, R. de Simone.

Periodic scheduling of marked graphs using balanced binary words, in: Theoretical Computer Science, November 2012, vol. 458, n^o 2, p. 113–130. [ DOI : 10.1016/j.tcs.2012.08.012 ]

http://hal.inria.fr/hal-00764076
21S. Touati, J. Worms, S. Briais.

The Speedup-Test: a statistical methodology for program speedup analysis and computation, in: Concurrency and Computation: Practice and Experience, 2012.

http://dx.doi.org/10.1002/cpe.2939

International Conferences with Proceedings

22J. Deantoni, F. Mallet.

TimeSquare: Treat your Models with Logical Time, in: TOOLS - 50th International Conference on Objects, Models, Components, Patterns - 2012, Prague, Czech Republic, C. A. Furia, S. Nanz (editors), Lecture Notes in Computer Science - LNCS, Springer, May 2012, vol. 7304, p. 34-41. [ DOI : 10.1007/978-3-642-30561-0_4 ]

http://hal.inria.fr/hal-00688590
23M. Djemal, F. Pêcheux, D. Potop-Butucaru, R. de Simone, F. Wajsbürt, Z. Zhang.

Programmable Routers for Efficient Mapping of Applications onto NoC-based MPSoCs, in: DASIP International Conference on Design and Architecture for Signal and Image Processing, IEEE, October 2012.
24A. Goknil, M.-A. Peraldi-Frati.

A DSL for Specifying Timing Requirements, in: MoDRE- 2sd International Model-Driven Requirements Engineering (MoDRE) Workshop, Chicago, United States, IEEE Digital Library, September 2012.

http://hal.inria.fr/hal-00757168
25C. Gomez, J. Deantoni, F. Mallet.

Multi-View Power Modeling based on UML, MARTE and SysML, in: SEAA - 38th Euromicro Conference on Software Engineering and Advanced Applications, Cesme, Turkey, October 2012, p. 17-20. [ DOI : 10.1109/SEAA.2012.66 ]

http://hal.inria.fr/hal-00720735
26S. Kuntz, M.-A. Peraldi-Frati, H. Blom, D. Karlsson.

Timing Modeling with AUTOSAR. Current State and Future Directions, in: DATE 2012. Design Automation & Test in Europe, Dresden, Germany, March 2012.

http://hal.inria.fr/hal-00667070
27Z. Liu, J. Liu, J. He, F. Mallet, Z. Miaomiao.

Formal Specification of Hybrid MARTE Statecharts, in: Sixth International Symposium on Theoretical Aspects of Software Engineering, Beijing, China, IEEE, July 2012. [ DOI : 10.1109/TASE.2012.26 ]

http://hal.inria.fr/hal-00764044
28F. Mallet.

Automatic Generation of Observers from MARTE/CCSL, in: International Symposium on Rapid System Prototyping, Tampere, Finland, IEEE, 2013.

http://hal.inria.fr/hal-00764066
29M. Marouf, L. George, Y. Sorel.

Schedulability analysis for a combination of non-preemptive strict periodic tasks and preemptive sporadic tasks, in: ETFA'12 - 17th IEEE International Conference on Emerging Technologies and Factory Automation, Kraków, Poland, IEEE, September 2012.

http://hal.inria.fr/hal-00737917
30J.-V. Millo, R. de Simone.

Refining cellular automata with routing constraints, in: Automata & JAC (Exploratory track), E. Formenti (editor), September 2012, vol. 2.
31J.-V. Millo, S. Ramesh.

Relating Requirement and Design Variabilities, in: Proceedings of the international workshop on Software Quality and Management (SQAM'12), December 2012.
32S. Mohalik, S. Ramesh, J.-V. Millo, Krishna Shankara. Narayanan, Ganesh Khandu. Narwane.

Tracing SPLs precisely and efficiently, in: Proceedings of the 16th International Software Product Line Conference - Volume 1, New York, NY, USA, SPLC '12, ACM, 2012, p. 186–195.

http://doi.acm.org/10.1145/2362536.2362562
33M.-A. Peraldi-Frati, A. Goknil, M. Adedjouma, P.-Y. Gueguen.

Modeling a BSG-E Automotive System with the Timing Augmented Description language., in: ISOLA 2012 -5th International Symposium On Leveraging Applications of Formal Methods, Verification and Validation, Amirandes, Héraklion, Greece, TU Dortmund - EASST, October 2012, p. 111-125.

http://hal.inria.fr/hal-00757185
34M.-A. Peraldi-Frati, A. Goknil, J. Deantoni, J. Nordlander.

A timing model for specifying multi clock automotive systems. The Timing Augmented Description Language V2, in: ICECCS 2012 : International Conference on Engineering of Complex Computer Systems, Paris, France, IEEE, July 2012, 10 pages p.

http://hal.inria.fr/hal-00687562
35M.-A. Peraldi-Frati, D. Karlsson, A. Hamann, S. Kuntz, J. Nordlander.

The TIMMO-2-USE project: Time modeling and analysis to use, in: ERTS2012 International Congres on Embedded Real Time Software and Systems, Toulouse, France, February 2012.

http://hal.inria.fr/hal-00649781
36M. Qamhieh, S. Midonnet, L. George.

A Parallelizing Algorithm for Real-Time Tasks of Directed Acyclic Graphs Model, in: RTAS'12 : The 18th IEEE Real-Time and Embedded Technology and Applications Symposium. Work-In-Progress Session, Beijing, China, April 2012, p. 45-48.

http://hal.inria.fr/hal-00695818

National Conferences with Proceeding

37D. De Rauglaudre.

Vérification formelle de conditions d'ordonnancabilité de tâches temps réel périodiques strictes, in: JFLA - Journées Francophones des Langages Applicatifs - 2012, Carnac, France, February 2012.

http://hal.inria.fr/hal-00665929

Scientific Books (or Scientific Book chapters)

38C. Glitia, J. Deantoni, F. Mallet.

Logical Time @ Work: Capturing Data Dependencies and Platform Constraints, in: System Specification and Design Languages, Lecture Notes in Electrical Engineering, Springer New York, 2012, vol. 106, p. 223–238. [ DOI : 10.1007/978-1-4614-1427-8_14 ]

http://hal.inria.fr/hal-00651864

Internal Reports

39T. Carle, D. Potop-Butucaru, Y. Sorel, D. Lesens.

From dataflow specification to multiprocessor partitioned time-triggered real-time implementation, Inria, October 2012, n^o RR-8109.

http://hal.inria.fr/hal-00742908
40J. Deantoni, F. Mallet.

ECL: the Event Constraint Language, an Extension of OCL with Events, Inria, July 2012, n^o RR-8031, 24 p.

http://hal.inria.fr/hal-00721169
41C. Gomez, J. Deantoni, F. Mallet.

Multi-View Power Modeling based on UML MARTE and SysML, Inria, April 2012, n^o RR-7934, 19 p.

http://hal.inria.fr/hal-00688853
42F. Mallet, L. Yin.

Correct Transformation from CCSL to Promela for verification, Inria, January 2012, n^o RR-7491, 33 p.

http://hal.inria.fr/hal-00667849
43J.-V. Millo, R. de Simone.

Periodic scheduling of marked graphs using balanced binary words, Inria, February 2012, n^o RR-7891, 33 p.

http://hal.inria.fr/hal-00672606
44J.-V. Millo, R. de Simone.

Refining cellular automata with routing constraints, Inria, August 2012, n^o RR-8051, 15 p.

http://hal.inria.fr/hal-00725878
45J.-V. Millo, S. Ramesh, Krishna Shankara. Narayanan, Ganesh Khandu. Narwane.

Compositional Verification of Evolving SPL, Inria, October 2012, n^o RR-8125, 34 p.

http://hal.inria.fr/hal-00747533
46L. Yin, J. Deantoni, F. Mallet, R. de Simone.

Schedulability analysis by exhaustive state space construction: translating CCSL to transition-based Generalized Buchi Automata, Inria, October 2012, n^o RR-8102, 22 p.

http://hal.inria.fr/hal-00743874

References in notes

47F. Baccelli, G. Cohen, Geert Jan. Olsder, Jean-Pierre. Quadrat.

Synchronization and Linearity: an algebra for discrete event systems, John Wiley & Sons, 1992.

http://cermics.enpc.fr/~cohen-g/SED/book-online.html
48A. Benveniste, G. Berry.

The Synchronous Approach to Reactive and Real-Time Systems, in: Proceedings of the IEEE, September 1991, vol. 79, n^o 9, p. 1270-1282.
49J. Carlier, P. Chrétienne.

Problèmes d'ordonnancement, Masson, 1988.
50L. Carloni, K. McMillan, A. Sangiovanni-Vincentelli.

Theory of Latency-Insensitive Design, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001.
51A. Cohen, M. Duranton, C. Eisenbeis, C. Pagetti, F. Plateau, M. Pouzet.

N-Synchronous Kahn Networks: a Relaxed Model of Synchrony for Real-Time Systems, in: ACM International Conference on Principles of Programming Languages (POPL'06), Charleston, South Carolina, USA, January 2006.
52J.B. Dennis.

First Version of a Dataflow Procedure Language, in: Lecture Notes in Computer Sci., Springer-Verlag, 1975, vol. 19, p. 362-376.
53S. Edwards.

Languages for Digital Embedded Systems, Kluwer, 2000.
54N. Halbwachs.

Synchronous Programming of Reactive Systems, in: Computer Aided Verification, 1998, p. 1-16.

http://www-verimag.imag.fr/~halbwach/newbook.pdf
55H. Heinecke.

AUTOSAR, an industrywide initiative to manage the complexity of emerging Automotive E/E-Architecture, in: Electronic Systems for Vehicles 2003, VDI Congress, Baden-Baden, 2003.
56Edward A. Lee, D. G. Messerschmitt.

Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing, in: IEEE Trans. Computers, 1987.
57C.L. Liu, J.W. Layland.

Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, in: Journal of the ACM, 1973.

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