Bibliography

Publications of the year

Articles in International Peer-Reviewed Journals

1Y. Chen, S. Fang, L. Eeckhout, O. Temam, C. Wu.

Deconstructing Iterative Optimization, in: ACM Transactions on Architecture and Code Optimization (TACO), 2012.
2H. Li, W. He, Y. Chen, L. Eeckhout, O. Temam, C. Wu.

SWAP: Parallelization through Algorithm Substitution, in: IEEE Micro, Special Issue on Parallelization of Sequential Code, 2012.

International Conferences with Proceedings

3T. Chen, Y. Chen, M. Duranton, Q. Guo, A. Hashmi, M. Lipasti, A. Nere, S. Qiu, M. Sebag, O. Temam.

BenchNN: On the Broad Potential Application Scope of Hardware Neural Network Accelerators, in: IEEE, International Symposium on Workload Characterization (IISWC), San Diego, CA, November 2012.
4T. Chen, Y. Chen, Q. Guo, O. Temam, Y. Wu, W. Hu.

Statistical Performance Comparisons of Computers, in: IEEE, International Symposium on High-Performance Computer Architecture (HPCA), New Orleans, Louisiana, February 2012.
5Y. Chen, S. Fang, L. Eeckhout, O. Temam, C. Wu.

Iterative Optimization for the Data Center, in: ACM/IEEE, International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS), London, UK, March 2012.
6A. Joubert, B. Belhadj, O. Temam, R. Heliot.

Hardware Spiking Neurons Design: Analog or Digital?, in: IEEE, International Joint Conference on Neural Networks (IJCNN), Brisbane, Australia, June 2012.
7A. Joubert, M. Duranton, B. Belhadj, O. Temam, R. Heliot.

Capacitance of TSVs in 3D Stacked Chips a Problem? Not for Neuromorphic Systems, in: Design Automation Conference (DAC), WACI session, San Francisco, June 2012.
8O. Temam.

A Defect-Tolerant Accelerator for Emerging High-Performance Applications, in: ACM/IEEE, International Symposium on Computer Architecture (ISCA), Portland, Oregon, June 2012.

References in notes

9S. Y. Borkar, P. Dubey, K. C. Kahn, D. J. Kuck, H. Mulder, E. R. M. Ramanathan, V. Thomas, I. Corporation, S. S. Pawlowski.

Intel ® Processor and Platform Evolution for the Next Decade Executive Summary, 2006.
10L. N. Chakrapani, B. E. S. Akgul, S. Cheemalavagu, P. Korkmaz, K. V. Palem, B. Seshasayee.

Ultra-efficient (embedded) SOC architectures based on probabilistic CMOS (PCMOS) technology, in: Design, Automation, and Test in Europe, Munich, 2006, 1110 p.
11S. Cheemalavagu, P. Korkmaz, K. V. Palem.

Ultra low-energy computing via probabilistic algorithms and devices: CMOS device primitives and the energy-probability relationship, in: International Conference on Solid State Devices, Tokyo, 2004, p. 2–4.
12L. Chua.

Memristor-The missing circuit element, in: IEEE Transactions on Circuit Theory, 1971, vol. 18, n^o 5, p. 507–519. [ DOI : 10.1109/TCT.1971.1083337 ]
13P. Fromherz, A. Stett.

Silicon-Neuron Junction: Capacitive Stimulation of an Individual Neuron on a Silicon Chip, in: Physical Review Letters, August 1995, vol. 75, n^o 8, p. 1670–1673. [ DOI : 10.1103/PhysRevLett.75.1670 ]
14H. Larochelle, D. Erhan, A. Courville, J. Bergstra, Y. Bengio.

An empirical evaluation of deep architectures on problems with many factors of variation, in: International Conference on Machine Learning, New York, New York, USA, ACM Press, 2007, p. 473–480. [ DOI : 10.1145/1273496.1273556 ]
15B. Liang, P. Dubey.

Recognition, Mining and Synthesis, in: Intel Technology Journal, 2005, vol. 09, n^o 02. [ DOI : 10.1535/itj.0902.f ]
16M. Muller.

Dark Silicon and the Internet, in: EE Times "Designing with ARM" virtual conference, 2010.
17T. Serre, L. Wolf, S. Bileschi, M. Riesenhuber, T. Poggio.

Robust object recognition with cortex-like mechanisms., in: IEEE transactions on pattern analysis and machine intelligence, March 2007, vol. 29, n^o 3, p. 411–26. [ DOI : 10.1109/TPAMI.2007.56 ]
18G. Snider.

Molecular-junction-nanowire-crossbar ... - Google Patent Search, 2008.
19R. S. Williams.

How We Found the Missing Memristor, in: IEEE Spectrum, 2008.

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