Bibliography

Major publications by the team in recent years

1A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.

The Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE Special issue on Modeling and Design of Embedded Systems, 2003, vol. 91, n^o 1.

http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.96.1117
2L. Besnard, T. Gautier, P. Le Guernic, J.-P. Talpin.

Compilation of Polychronous Data Flow Equations, in: Synthesis of Embedded Software, S. K. Shukla, J.-P. Talpin (editors), Springer, 2010, p. 1-40. [ DOI : 10.1007/978-1-4419-6400-7_1 ]

http://hal.inria.fr/inria-00540493
3L. Besnard, T. Gautier, M. Moy, J.-P. Talpin, K. Johnson, F. Maraninchi.

Automatic translation of C/C++ parallel code into synchronous formalism using an SSA intermediate form, in: Electronic Communication of the European Association of Software Science and Technology, 2009, vol. 23, Automated Verification of Critical Systems 2009.

http://journal.ub.tu-berlin.de/eceasst/article/view/312/301
4C. Brunette, J.-P. Talpin, A. Gamatié, T. Gautier.

A metamodel for the design of polychronous systems, in: The Journal of Logic and Algebraic Programming, 2009, vol. 78, n^o 4, p. 233 - 259, IFIP WG1.8 Workshop on Applying Concurrency Research in Industry. [ DOI : 10.1016/j.jlap.2008.11.005 ]

http://www.sciencedirect.com/science/article/pii/S1567832608000957
5A. Gamatié, T. Gautier, P. Le Guernic, J.-P. Talpin.

Polychronous Design of Embedded Real-Time Applications, in: ACM Transactions on Software Engineering and Methodology (TOSEM), April 2007, vol. 16, n^o 2.

http://doi.acm.org/10.1145/1217295.1217298
6A. Gamatié, T. Gautier.

The Signal Synchronous Multiclock Approach to the Design of Distributed Embedded Systems, in: IEEE Transactions on Parallel and Distributed Systems, 2010, vol. 21, n^o 5, p. 641-657. [ DOI : 10.1109/TPDS.2009.125 ]

http://hal.inria.fr/inria-00522794
7A. Gamatié, T. Gautier, P. Le Guernic.

Synchronous design of avionic applications based on model refinements, in: Journal of Embedded Computing (IOS Press), 2006, vol. 2, n^o 3-4, p. 273-289.

http://hal.archives-ouvertes.fr/hal-00541523
8P. Le Guernic, J.-P. Talpin, J.-C. Le Lann.

Polychrony for system design, in: Journal of Circuits, Systems and Computers, Special Issue on Application Specific Hardware Design, June 2003, vol. 12, n^o 03.

http://hal.inria.fr/docs/00/07/18/71/PDF/RR-4715.pdf
9D. Potop-Butucaru, Y. Sorel, R. de Simone, J.-P. Talpin.

From Concurrent Multi-clock Programs to Deterministic Asynchronous Implementations, in: Fundamenta Informaticae, January 2011, vol. 108, n^o 1-2, p. 91–118.

http://dl.acm.org/citation.cfm?id=2362088.2362094
10J.-P. Talpin, P. Le Guernic, S. Shukla, R. Gupta.

A compositional behavioral modeling framework for embedded system design and conformance checking, in: International Journal of Parallel Programming, December 2005, vol. 33, n^o 6, p. 613-643. [ DOI : 10.1007/s10766-005-8907-y ]

http://hal.archives-ouvertes.fr/hal-00541986

Publications of the year

Articles in International Peer-Reviewed Journals

11J. Brandt, M. Gemünde, K. Schneider, S. Shukla, J.-P. Talpin.

Representation of synchronous, asynchronous, and polychronous components by clocked guarded actions, in: Design Automation for Embedded Systems, 2012. [ DOI : 10.1007/s10617-012-9087-9 ]

http://hal.inria.fr/hal-00763334
12J. Brandt, M. Gemünde, K. Schneider, S. Shukla, J.-P. Talpin.

Embedding Polychrony into Synchrony, in: IEEE Transactions on Software Engineering, 2013.

http://hal.inria.fr/hal-00763317
13J.-P. Talpin, J. Ouy, T. Gautier, L. Besnard, P. Le Guernic.

Compositional design of isochronous systems, in: Science of Computer Programming, February 2012, vol. 77, n^o 2, p. 113-128. [ DOI : 10.1016/j.scico.2010.06.006 ]

http://hal.archives-ouvertes.fr/hal-00768341

International Conferences with Proceedings

14A. Bouakaz, J.-P. Talpin, J. Vitek.

Affine Data-Flow Graphs for the Synthesis of Hard Real-Time Applications, in: Proceedings of the 2012 12th International Conference on Application of Concurrency to System Design, Hamburg, Germany, ACM, 2012, p. 183-192. [ DOI : 10.1109/ACSD.2012.16 ]

http://hal.inria.fr/hal-00763387
15Y. Ma, H. Yu, T. Gautier, P. Le Guernic, J.-P. Talpin, L. Besnard, M. Heitz.

Toward Polychronous Analysis and Validation for Timed Software Architectures in AADL, in: The Design, Automation, and Test in Europe (DATE) conference, Grenoble, France, March 2013, 6 p.

http://hal.inria.fr/hal-00763379
16V. C. Ngo, L. Besnard, T. Gautier, P. Le Guernic, J.-P. Talpin.

Formal Verification of Compiler Transformations on Polychronous Equations, in: International Conference on Integrated Formal Methods, Pisa, Italy, CNR/ISTI Italy, June 2012.

http://hal.inria.fr/hal-00730393
17J.-P. Talpin, J. Brandt, M. Gemünde, K. Schneider, S. Shukla.

Constructive Polychronous Systems, in: Logical Foundations of Computer Science, San Diego, CA, United States, S. Artemov, A. Nerode (editors), Lecture Notes in Computer Science, Springer, 2013, vol. 7734.

http://hal.inria.fr/hal-00763371

Internal Reports

18V. C. Ngo, J.-P. Talpin, T. Gautier, P. Le Guernic, L. Besnard.

Formal Verification of Synchronous Data-flow Compilers, Inria, 2012, n^o RR-7921.

http://hal.inria.fr/hal-00685633
19V. C. Ngo, J.-P. Talpin, P. Le Guernic.

Formal Verification of Transformations on Abstract Clocks in Synchronous Compilers, Inria, September 2012, n^o RR-8064.

http://hal.inria.fr/hal-00730926

References in notes

20Cost-efficient methods and processes for safety relevant embedded systems (CESAR project).

http://www.cesarproject.eu/
21Open Platform for the Engineering of Embedded Systems (OPEES Project).

http://www.opees.org/
22OpenEmbeDD website, 2009.

http://openembedd.org
23Polychrony Update Site for Eclipse plug-ins, 2009.

http://www.irisa.fr/espresso/Polychrony/update/
24The Polychrony Toolset.

http://www.irisa.fr/espresso/Polychrony/
25TopCased website, 2009.

http://www.topcased.org
26 Airlines Electronic Engineering Committee.

ARINC Report 651-1: Design Guidance for Integrated Modular Avionics, Aeronautical radio, Inc., Annapolis, Maryland, 1997.
27 Airlines Electronic Engineering Committee.

ARINC Specification 653: Avionics Application Software Standard Interface, Aeronautical radio, Inc., Annapolis, Maryland, 1997.
28P. Amagbegnon, L. Besnard, P. Le Guernic.

Implementation of the data-flow synchronous language SIGNAL, in: ACM SIGPLAN Notices, June 1995, vol. 30, n^o 6, p. 163-173. [ DOI : 10.1145/223428.207134 ]

http://hal.archives-ouvertes.fr/hal-00544128
29C. André, F. Mallet, R. de Simone.

Modeling Time(s), in: ACM/IEEE Int. Conf. on Model Driven Engineering Languages and Systems (MoDELS/UML'07), TN, USA, LNCS 4735, Springer, October 2007, p. 559–573.
30C. Baier, J.-P. Katoen.

Principles of model checking, in: The MIT Press, 2008.
31C. Barrett, S. Ranise, A. Stump, C. Tinelli.

The Satisfiability Modulo Theories Library (SMT-LIB), 2008.

http://www.SMT-LIB.org
32A. Benveniste, B. Caillaud, P. Le Guernic.

From synchrony to asynchrony, in: CONCUR'99, Concurrency Theory, 10th International Conference, J. C. M. Baeten, S. Mauw (editors), Lecture Notes in Computer Science, Springer, August 1999, vol. 1664, p. 162–177.

http://hal.inria.fr/inria-00073032
33A. Benveniste, P. Caspi, L. Carloni, A. Sangiovanni-Vincentelli.

Heterogeneous Reactive Systems Modeling and Correct-by-Construction Deployment, in: Embedded Software Conference (EMSOFT'03), Springer Verlag, 2003.
34A. Benveniste, P. Le Guernic, C. Jacquemot.

Synchronous programming with events and relations: the Signal language and its semantics, in: Science of Computer Programming, September 1991, vol. 16, n^o 2, p. 103-149.

http://dx.doi.org/10.1016/0167-6423(91)90001-E
35L. Besnard, T. Gautier, P. Le Guernic.

SIGNAL V4-Inria version: Reference Manual, 2009.

http://www.irisa.fr/espresso/Polychrony
36A. Biere, M. Heule, H. van Maaren, T. Walsh.

Handbook of satisfiability: Volume 185 Frontiers in Artificial Intelligence and Applications, in: ISBN 978-1-5860-3929-5, 2009.
37M. Bozzano, A. Cimatti, J.-P. Katoen, V. Nguyen, T. Noll, M. Roveri.

Safety, Dependability, and Performance Analysis of Extended AADL Models, in: The Computer Journal, 2011, vol. 54, n^o 5, p. 754–775.
38B. Dutertre, L. de Moura.

Yices sat-solver, 2009.

http://yices.csl.sri.com
39B. Dutertre, M. Le Borgne, H. Marchand.

SIGALI : un système de calcul formel pour la vérification de programmes SIGNAL, 1998, Manuel d'utilisation.
40 Esterel Technologies.

SCADE Suite.

http://www.esterel-technologies.com/products/scade-suite/
41A. Gamatié.

Designing Embedded Systems with the SIGNAL Programming Language, Springer, 2009.

http://www.springer.com/engineering/circuits+%26+systems/book/978-1-4419-0940-4
42T. Gautier, P. Le Guernic.

Code generation in the SACRES project, in: Towards System Safety, Proceedings of the Safety-critical Systems Symposium, SSS'99, Huntingdon, Royaume-Uni, Springer, 1999, p. 127-149.

http://hal.archives-ouvertes.fr/hal-00543824
43 Inria AOSTE TEAM.

SynDEx.

http://www-rocq.inria.fr/syndex/
44 Inria AOSTE TEAM.

TimeSquare.

http://timesquare.inria.fr/
45E. Jahier, N. Halbwachs, P. Raymond, X. Nicollin, D. Lesens.

Virtual execution of AADL models via a translation into synchronous programs, in: ACM & IEEE international conference on Embedded software (EMSOFT), 2007.
46G. Kahn.

The Semantics of a Simple Language for Parallel Programming, in: IFIP Congress, 1974, p. 471-475.
47A. Kountouris, P. Le Guernic.

Profiling of SIGNAL programs and its application in the timing evaluation of design implementations, in: IEE Colloquium on the Hardware-Software Cosynthesis for Reconfigurable, Bristol, Royaume-Uni, The Institution of Electrical Engineers, 1996, p. 6/1-6/9. [ DOI : 10.1049/ic:19960225 ]

http://hal.archives-ouvertes.fr/hal-00544253
48P. Le Guernic, T. Gautier, M. Le Borgne, C. Le Maire.

Programming Real-Time Applications with Signal, in: Proceedings of the IEEE, 1991, vol. 79, n^o 9, p. 1321-1336. [ DOI : 10.1109/5.97301 ]

http://hal.inria.fr/inria-00540460
49P. Le Guernic, T. Gautier, M. Le Borgne, C. Le Maire.

Programming Real-Time Applications with Signal, in: Proceedings of the IEEE, Septembre 1991, vol. 79, n^o 9, p. 1321–1336.
50O. Maffeis, P. Le Guernic.

Distributed Implementation of SIGNAL: Scheduling & Graph Clustering, in: Formal Techniques in Real-Time and Fault-Tolerant Systems, Lübeck, Allemagne, LNCS vol. 863, Springer-Verlag, 1994, p. 547-566.

http://hal.archives-ouvertes.fr/hal-00544101
51O. Maler, A. Pnueli, J. Sifakis.

On the Synthesis of Discrete Controllers for timed Systems, in: Proceedings STACS'95, Lecture Notes in Computer Science, 1995, vol. 900, p. 229–242.
52H. Marchand, P. Bournai, M. Le Borgne, P. Le Guernic.

Synthesis of Discrete-Event Controllers based on the Signal Environment, in: Discrete Event Dynamic Systems, October 2000, vol. 10, n^o 4, p. 325-346. [ DOI : 10.1023/A:1008311720696 ]

http://hal.archives-ouvertes.fr/hal-00546147
53 OBJECT MANAGEMENT GROUP (OMG).

UML Profile for MARTE: Modeling and Analysis of Real-Time Embedded Systems, v1.1, June 2011.

http://www.omg.org/spec/MARTE/1.1/PDF/
54A. Pnueli, M. Siegel, E. Singerman.

Translation validation: From SIGNAL to C, in: Correct Sytem Design Recent Insights and Advances, 2000, p. 231-255.
55A. Pnueli, M. Siegel, E. Singerman.

Translation validation, in: Proceedings of TACAS'98, 1998, p. 151-166.
56P. Ramadge, W. Wonham.

The Control of Discrete Event Systems, in: Proceedings of the IEEE, Special issue on Dynamics of Discrete Event Systems, 1989, vol. 77, n^o 1, p. 81–98.
57F. Singhoff, J. Legrand, L. Nana, L. Marcé.

Scheduling and memory requirements analysis with AADL, in: ACM SIGAda international conference on ADA (SigAda'05), 2005.

http://doi.acm.org/10.1145/1103846.1103847
58I. Smarandache, T. Gautier, P. Le Guernic.

Validation of Mixed Signal-Alpha Real-Time Systems through Affine Calculus on Clock Synchronisation Constraints, in: FM'99 - Formal Methods, World Congress on Formal Methods in the Development of Computing Systems, Toulouse, France, LNCS vol. 1709, Springer, 1999, p. 1364-1383. [ DOI : 10.1007/3-540-48118-4_22 ]

http://hal.archives-ouvertes.fr/hal-00548887
59A. Stump, M. Deters.

http://www.smtcomp.org/2009 , 2009.
60H. Yu, Y. Ma, Y. Glouche, J.-P. Talpin, L. Besnard, T. Gautier, P. Le Guernic, A. Toom, O. Laurent.

System-level Co-simulation of Integrated Avionics Using Polychrony, in: ACM Symposium On Applied Computing, TaiChung, Taïwan, March 2011.

http://hal.inria.fr/inria-00536907/en/
61H. Yu, J.-P. Talpin, L. Besnard, T. Gautier, F. Mallet, C. André, R. de Simone.

Polychronous Analysis of Timing Constraints in UML MARTE, in: IEEE International Workshop on Model-Based Engineering for Real-Time Embedded Systems Design, Parador of Carmona, Espagne, 2010, 7 p. p.

http://hal.inria.fr/inria-00497249
62H. Yu, J.-P. Talpin, L. Besnard, T. Gautier, H. Marchand, P. Le Guernic.

Polychronous Controller Synthesis from MARTE CCSL Timing Specifications, in: ACM/IEEE Ninth International Conference on Formal Methods and Models for Codesign (MEMOCODE), Cambridge, Royaume-Uni, July 2011.

http://hal.inria.fr/inria-00594942/en/
63L. de Moura, N. Bjorner.

Satisfiability Modulo Theories: An appetizer, in: Brazilian Symposium on Formal Methods, 2009.

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