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AOSTE - 2014
AOSTE - 2014
Project-Team Aoste
Members
Overall Objectives
Research Program
Application Domains
New Software and Platforms
New Results
Bilateral Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography


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Bibliography

Major publications by the team in recent years
  • 1C. André.

    Syntax and Semantics of the Clock Constraint Specification Language (CCSL), Inria, 05 2009, no RR-6925, 37 p.

    http://hal.inria.fr/inria-00384077/en/
  • 2C. André, J. Deantoni, F. Mallet, R. de Simone.

    The Time Model of Logical Clocks available in the OMG MARTE profile, in: Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, S. K. Shukla, J.-P. Talpin (editors), Springer Science+Business Media, LLC 2010, Jul 2010, pp. 201–227, Chapter 7.
  • 3C. André, F. Mallet, R. de Simone.

    Modeling Time(s), in: MoDELS'2007 10th Intern. Conf. on Model Driven Engineering Languages and Systems, 2007.
  • 4A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.

    Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE, January 2003.
  • 5J. Boucaron, A. Coadou, R. de Simone.

    Formal Modeling of Embedded Systems with Explicit Schedules and Routes, in: Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, S. K. Shukla, J.-P. Talpin (editors), Springer Science+Business Media, LLC 2010, Jul 2010, pp. 41–78, Chapter 2.
  • 6J. Boucaron, R. de Simone, J.-V. Millo.

    Latency-insensitive design and central repetitive scheduling, in: MEMOCODE, 2006, pp. 175-183.

    http://dx.doi.org/10.1109/MEMCOD.2006.1695923
  • 7L. Cucu-Grosjean, N. Pernet, Y. Sorel.

    Periodic real-time scheduling: from deadline-based model to latency-based model, in: Annals of Operations Research, 2007.

    http://www-rocq.inria.fr/syndex/publications/pubs/aor07/aor07.pdf
  • 8T. Grandpierre, C. Lavarenne, Y. Sorel.

    Optimized Rapid Prototyping For Real-Time Embedded Heterogeneous multiprocessors, in: Proceedings of 7th International Workshop on Hardware/Software Co-Design, CODES'99, 1999.
  • 9T. Grandpierre, Y. Sorel.

    From Algorithm and Architecture Specification to Automatic Generation of Distributed Real-Time Executives: a Seamless Flow of Graphs Transformations, in: Proceedings of First ACM and IEEE International Conference on Formal Methods and Models for Codesign, MEMOCODE'03, Mont Saint-Michel, France, June 2003.

    http://www-rocq.inria.fr/syndex/publications/pubs/memocode03/memocode03.pdf
  • 10P. Meumeu Yomsi, Y. Sorel.

    Extending Rate Monotonic Analysis with Exact Cost of Preemptions for Hard Real-Time Systems, in: Proceedings of 19th Euromicro Conference on Real-Time Systems, ECRTS'07, Pisa, Italy, July 2007.

    http://www-rocq.inria.fr/syndex/publications/pubs/ecrts07/ecrts07.pdf
  • 11D. Potop-Butucaru, Benoît. Caillaud.

    Correct-by-Construction Asynchronous Implementation of Modular Synchronous Specifications, in: Fundam. Inf., January 2007, vol. 78, pp. 131–159.

    http://portal.acm.org/citation.cfm?id=1366007.1366013
  • 12D. Potop-Butucaru, R. de Simone, Y. Sorel.

    From Synchronous Specifications to Statically-Scheduled Hard Real-Time Implementations, in: Synthesis of Embedded Software: Frameworks and Methodologies for Correctness by Construction, S. K. Shukla, J.-P. Talpin (editors), Springer Science+Business Media, LLC 2010, Jul 2010, pp. 229–262, Chapter 8.
  • 13D. Potop-Butucaru, S. Edwards, G. Berry.

    Compiling Esterel, Springer, 2007.
  • 14D. Potop-Butucaru, R. de Simone.

    Optimizations for Faster Execution of Esterel Programs, in: MEMOCODE'03, 2003.
  • 15R. de Simone, D. Potop-Butucaru, Jean-Pierre. Talpin.

    The Synchronous Hypothesis and Synchronous Languages, in: Embedded Systems Handbook, CRC Press, 2005, chap. 8.
Publications of the year

Doctoral Dissertations and Habilitation Theses

Articles in International Peer-Reviewed Journals

  • 20S. Altmeyer, L. Cucu-Grosjean, R. Davis.

    Static Probabilistic Timing Analysis for Real-Time Systems using Random Replacement Caches, in: Real-Time Systems, 2015.

    https://hal.archives-ouvertes.fr/hal-01094370
  • 21T. Carle, D. Potop-Butucaru.

    Predicate-aware, makespan-preserving software pipelining of scheduling tables, in: ACM Transactions on Architecture and Code Optimization, 2014, vol. 11, pp. 1 - 26. [ DOI : 10.1145/2579676 ]

    https://hal.inria.fr/hal-01095123
  • 22B. Combemale, J. Deantoni, B. Baudry, R. France, J.-M. Jézéquel, J. Gray.

    Globalizing Modeling Languages, in: Computer, June 2014, pp. 10-13.

    https://hal.inria.fr/hal-00994551
  • 23R. Davis, T. Vardanega, J. Alexanderson, V. Francis, P. Mark, B. Ian, A.-A. Mikel, F. Wartel, L. Cucu-Grosjean, P. Mathieu, F. Glenn, F. J. Cazorla.

    PROXIMA: A Probabilistic Approach to the Timing Behaviour of Mixed-Criticality Systems, in: Ada User Journal, 2014, no 2, pp. 118-122.

    https://hal.archives-ouvertes.fr/hal-01094390
  • 24J.-V. Millo, E. Kofman, R. De Simone.

    Modeling and analyzing dataflow applications on NoC based many-cores architectures, in: ACM Transactions in Embedded Computing Systems, November 2014, 24 p.

    https://hal.archives-ouvertes.fr/hal-01097315

International Conferences with Proceedings

  • 25T. Carle, M. Djemal, D. Genius, F. Pêcheux, D. Potop-Butucaru, R. De Simone, F. Wajsbürt, Z. Zhang.

    Reconciling performance and predictability on a many-core through off-line mapping, in: 9th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC'2014), Montpellier, France, Proceedings ReCoSoC 2014, May 2014. [ DOI : 10.1109/ReCoSoC.2014.6861367 ]

    https://hal.inria.fr/hal-01095116
  • 26T. Carle, M. Djemal, D. Potop-Butucaru, R. De Simone.

    Static mapping of real-time applications onto massively parallel processor arrays, in: 14th International Conference on Application of Concurrency to System Design, Hammamet, Tunisia, Proceedings ACSD 2014, June 2014.

    https://hal.inria.fr/hal-01095130
  • 27A. Cohen, V. Perrelle, D. Potop-Butucaru, E. Soubiran, Z. Zhang.

    Mixed-criticality in Railway Systems: A Case Study on Signalling Application, in: Workshop on Mixed Criticality for Industrial Systems (WMCIS'2014), Paris, France, Proceedings WMCIS 2014, June 2014.

    https://hal.inria.fr/hal-01095111
  • 28J. Deantoni, P. Issa Diallo, C. Teodorov, J. Champeau, B. Combemale.

    Towards a Meta-Language for the Concurrency Concern in DSLs, in: Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 2015.

    https://hal.inria.fr/hal-01087442
  • 29A. Khecharem, C. Gomez, J. Deantoni, F. Mallet, R. De Simone.

    Execution of Heterogeneous Models for Thermal Analysis with a Multi-view Approach, in: FDL 2014 : Forum on specification and Design Languages, Munich, Germany, IEEE, October 2014.

    https://hal.inria.fr/hal-01060309
  • 30T. Koch, J. Holtmann, J. Deantoni.

    Generating EAST-ADL Event Chains from Scenario-Based Requirements Specifications, in: European Conference on Software Architecture, Vienna, Austria, P. Avgeriou, U. Zdun (editors), Lecture Notes in Computer Science, Springer International Publishing, August 2014, vol. 8627, pp. 146-153. [ DOI : 10.1007/978-3-319-09970-5_14 ]

    https://hal.inria.fr/hal-01059504
  • 31F. Mallet, Z. Grygoriy.

    Co-Algebraic Semantic Model for the Clock Constraint Specification Language, in: Formal Techniques for Safety-Critical Systems - ICFEM 2014, Luxem bourg, Luxembourg, Communications in Computer and Information Science, Springer, November 2014.

    https://hal.inria.fr/hal-01096688
  • 32F. Wartel, L. Kosmidis, A. G. Gogonel, B. Andrea, S. Zoe, B. Triquet, E. Quinones, L. Code, E. Mezzeti, B. Ian, J. Abella, L. Cucu-Grosjean, T. Vardanega, F. J. Cazorla.

    Timing Analysis of an Avionics Case Study on Complex Hardware/Software Platforms, in: Design, Automation and Test in Europe Conference and Exhibition (DATE), Grenoble, France, March 2015.

    https://hal.archives-ouvertes.fr/hal-01094399
  • 33Y. Zhang, F. Mallet, Y. Chen.

    Timed Automata Semantics of Spatio-Temporal Consistency Language STeC, in: International Symposium on Theoretical Aspects of Software Engineering, Changsa, China, IEEE Computer Society, September 2014, pp. 201-208. [ DOI : 10.1109/TASE.2014.10 ]

    https://hal.inria.fr/hal-01096687

National Conferences with Proceedings

Scientific Books (or Scientific Book chapters)

  • 35M.-A. Peraldi-Frati, C. Urtado (editors)

    CIEL 2014 : Conférence en IngénieriE du Logiciel, Actes de la troisième édition de CIEL 2014, Catherine Dubois, Nicole Levy and Conservatoire National des Arts et Métiers, CNAM, Paris, Paris, France, June 2014, 158 p.

    https://hal.inria.fr/hal-01094542
  • 36L. Cucu-Grosjean, A. G. Gogonel, M. Dorin.

    Focus sur l'ordonnancement probabiliste, in: Ordonnancement des systèmes temps réel, M. Chetto (editor), ISTE/Wiley, 2014.

    https://hal.archives-ouvertes.fr/hal-01094361
  • 37L. Cucu-Grosjean, A. G. Gogonel, M. Dorin.

    Probabilistic real-time scheduling, in: Reat-time Systems Scheduling, M. Chetto (editor), ISTE/Wiley, 2014.

    https://hal.archives-ouvertes.fr/hal-01094341
  • 38F. Mallet, M.-A. Peraldi-Frati, J. Deantoni, R. De Simone.

    UML MARTE Time Model and Its Clock Constraint Specification Language, in: Embedded Systems Design, A. Bagnato, L. S. Indrusiak, I. R. Quadri, M. Rossi (editors), Handbook of Research on, IGI Global, June 2014. [ DOI : 10.4018/978-1-4666-6194-3.ch002 ]

    https://hal.inria.fr/hal-01079039
  • 39B. Michel, S. Li, I. R. Quadri, E. Brosse, S. Andrey, E. Gaudin, F. Mallet, A. Goknil, G. David, K. Jari.

    Fostering Analysis from Industrial Embedded Systems Modeling, in: Handbook of Research on Embedded Systems Design, A. Bagnato, L. S. Indrusiak, I. R. Quadri, M. Rossi (editors), IGI Global, June 2014, pp. 283–300. [ DOI : 10.4018/978-1-4666-6194-3.ch011 ]

    https://hal.inria.fr/hal-01088439
  • 40D. Potop-Butucaru, Y. Sorel.

    Approche synchrone et ordonnancement, in: Ordonnancement dans les systèmes temps réel, M. Chetto (editor), ISTE, June 2014.

    https://hal.inria.fr/hal-01096245
  • 41D. Potop-Butucaru, Y. Sorel.

    Synchronous Approach and Scheduling, in: Real-time Systems Scheduling 2: Focuses, M. Chetto (editor), Wiley-ISTE, 2014. [ DOI : 10.1002/9781119042976.ch4 ]

    https://hal.inria.fr/hal-01096255
  • 42S. Touati, B. De Dinechin.

    Advanced Backend Code Optimization, ISTE, Wiley, May 2014, 384 p.

    https://hal.inria.fr/hal-01082649

Books or Proceedings Editing

  • 43B. Combemale, J. Deantoni, R. France (editors)

    GEMOC 2014 2nd International Workshop on The Globalization of Modeling Languages, CEUR-WS, September 2014, vol. 1236, 82 p.

    https://hal.inria.fr/hal-01074602

Internal Reports

  • 44J. Deantoni, C. André, R. Gascon.

    CCSL denotational semantics, Inria ; I3S, November 2014, no RR-8628, 29 p.

    https://hal.inria.fr/hal-01082274
  • 45J. Deantoni, P. I. Diallo, J. Champeau, B. Combemale, C. Teodorov.

    Operational Semantics of the Model of Concurrency and Communication Language, September 2014, no RR-8584, 23 p.

    https://hal.inria.fr/hal-01060601
References in notes
  • 46K. Asanovic, R. Bodik, B. C. Catanzaro, J. J. Gebis, K. Keutzer, D. A. Patterson, W. L. Plishker, J. Shalf, S. W. Williams, K. A. Yelick, M. J. Demmel, W. Plishker, J. Shalf, S. Williams, K. Yelick.

    The Landscape of Parallel Computing Research: A View from Berkeley, Technical Report, University of California, Berkeley, 2006.
  • 47F. Baccelli, G. Cohen, Geert Jan. Olsder, Jean-Pierre. Quadrat.

    Synchronization and Linearity: an algebra for discrete event systems, John Wiley & Sons, 1992.

    http://cermics.enpc.fr/~cohen-g/SED/book-online.html
  • 48A. Benveniste, G. Berry.

    The Synchronous Approach to Reactive and Real-Time Systems, in: Proceedings of the IEEE, September 1991, vol. 79, no 9, pp. 1270-1282.
  • 49J. Carlier, P. Chrétienne.

    Problèmes d'ordonnancement, Masson, 1988.
  • 50L. Carloni, K. McMillan, A. Sangiovanni-Vincentelli.

    Theory of Latency-Insensitive Design, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2001.
  • 51A. Cohen, M. Duranton, C. Eisenbeis, C. Pagetti, F. Plateau, M. Pouzet.

    N-Synchronous Kahn Networks: a Relaxed Model of Synchrony for Real-Time Systems, in: ACM International Conference on Principles of Programming Languages (POPL'06), Charleston, South Carolina, USA, January 2006.
  • 52J.B. Dennis.

    First Version of a Dataflow Procedure Language, in: Lecture Notes in Computer Science, Springer-Verlag, 1975, vol. 19, pp. 362-376.
  • 53S. Edwards.

    Languages for Digital Embedded Systems, Kluwer, 2000.
  • 54N. Halbwachs.

    Synchronous Programming of Reactive Systems, in: Computer Aided Verification, 1998, pp. 1-16.

    http://www-verimag.imag.fr/~halbwach/newbook.pdf
  • 55H. Heinecke.

    AUTOSAR, an industrywide initiative to manage the complexity of emerging Automotive E/E-Architecture, in: Electronic Systems for Vehicles 2003, VDI Congress, Baden-Baden, 2003.
  • 56Edward A. Lee, D. G. Messerschmitt.

    Static Scheduling of Synchronous Data Flow Programs for Digital Signal Processing, in: IEEE Trans. Computers, 1987.
  • 57C.L. Liu, J.W. Layland.

    Scheduling Algorithms for Multiprogramming in a Hard-Real-Time Environment, in: Journal of the ACM, 1973.


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