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Bibliography

Publications of the year

Articles in International Peer-Reviewed Journals

  • 1Q. Colombet, F. Brandner, A. Darte.

    Studying Optimal Spilling in the Light of SSA, in: ACM Transactions on Architecture and Code Optimization, 2014, pp. 25-34, forthcoming.

    https://hal.inria.fr/hal-01099016

Invited Conferences

  • 2A. Darte.

    Polyhedral Optimizations? Not Even Scared!, in: Jornadas Sarteco, Valladolid, Spain, Arturo González Escribano and Diego R. Llanos Ferraris, September 2014, Keynote speech.

    https://hal.inria.fr/hal-01099290

International Conferences with Proceedings

  • 3A. Darte, A. Isoard.

    Parametric Tiling with Inter-Tile Data Reuse, in: 4th International Workshop on Polyhedral Compilation Techniques (IMPACT'14), Vienna, Austria, S. Rajopadhye, S. Verdoolaege (editors), January 2014.

    https://hal.archives-ouvertes.fr/hal-00915831
  • 4A. Darte, A. Isoard.

    Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes, in: 24th International Conference on Compiler Construction (CC'15), part of ETAPS'15, London, United Kingdom, April 2015.

    https://hal.inria.fr/hal-01099017
  • 5P. Feautrier.

    The Power of Polynomials , in: 5th International Workshop on Polyhedral Compilation Techniques (IMPACT'15), Amsterdam, Netherlands, A. Jimborean, A. Darte (editors), January 2015.

    https://hal.inria.fr/hal-01094787
  • 6P. Feautrier, E. Violard, A. Ketterlin.

    Improving X10 Program Performances by Clock Removal, in: 23rd International Conference on Compiler Construction (CC’14), part of ETAPS’14, Grenoble, France, April 2014.

    https://hal.inria.fr/hal-00924206
  • 7G. Iooss, C. Alias, S. Rajopadhye.

    On Program Equivalence with Reductions, in: 21st International Static Analysis Symposium (SAS'14), Munich, Germany, September 2014.

    https://hal.inria.fr/hal-01096110
  • 8G. Iooss, S. Rajopadhye, C. Alias, Y. Zou.

    CART: Constant Aspect Ratio Tiling, in: 4th International Workshop on Polyhedral Compilation Techniques (IMPACT’14), Vienna, Austria, S. Rajopadhye, S. Verdoolaege (editors), January 2014.

    https://hal.archives-ouvertes.fr/hal-00915827
  • 9H. Nazaré, I. Maffra, W. Santos, L. Oliveira, F. Pereira, L. Gonnord.

    Validation of Memory Accesses Through Symbolic Analyses, in: ACM International Conference on Object Oriented Programming Systems Languages & Applications (OOPSLA'14), Portland, Oregon, United States, October 2014, pp. 791-809.

    https://hal.inria.fr/hal-01006209
  • 10R. E. Rodrigues, P. Alves, F. Pereira, L. Gonnord.

    Real-World Loops are Easy to Predict: A Case Study, in: Workshop on Software Termination (WST'14), Vienne, Austria, July 2014.

    https://hal.inria.fr/hal-01006208

Internal Reports

  • 11A. Darte, A. Isoard.

    Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes, LIP - ENS Lyon ; CNRS ; Inria ; UCBL, January 2015, no RR-8671, 28 p.

    https://hal.inria.fr/hal-01103460

Patents

  • 12C. Alias, A. Plesco.

    Procédé de synthèse de circuits, dispositif et programme d’ordinateur associés, April 2014, no FR1453308.

    https://hal.inria.fr/hal-01096129

Other Publications

  • 13P. Feautrier.

    U. Banerjee (editor), Author Retrospective for Array Expansion, Array Shrinking, or There and Back Again, ACM, 2014, 1 p, ACM International Conference on Supercomputing (ICS) 25th Anniversary Volume.

    https://hal.inria.fr/hal-01099746
  • 14A. Isoard.

    Data-reuse Optimizations for Pipelined Tiling with Parametric Tile Sizes, August 2014, 23rd International Conference on Parallel Architectures and Compilation Techniques (PACT'14).

    https://hal.inria.fr/hal-01111393
References in notes
  • 15C. Alias, A. Darte, P. Feautrier, L. Gonnord.

    Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs, in: 17th International Static Analysis Symposium (SAS'10), Perpignan, France, ACM press, September 2010, pp. 117-133.
  • 16C. Alias, A. Darte, P. Feautrier, L. Gonnord.

    Rank: A Tool to Check Program Termination and Computational Complexity, in: International Workshop on Constraints in Software Testing Verification and Analysis (CSTVA'13), Luxembourg, March 2013, 238 p.

    http://hal.inria.fr/hal-00801571
  • 17C. Alias, A. Darte, A. Plesco.

    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: International Conference on Design, Automation and Test in Europe (DATE'13), Grenoble, France, March 2013, pp. 575-580.
  • 18G. Andrieu, C. Alias, L. Gonnord.

    SToP: Scalable Termination Analysis of (C) Programs, in: International Workshop on Tools for Automatic Program Analysis (TAPAS'12), Deauville, France, September 2012, (tool presentation).

    http://hal.inria.fr/hal-00760926
  • 19A. M. Ben-Amram, S. Genaim.

    Ranking Functions for Linear-Constraint Loops, in: Journal of the ACM, July 2014, vol. 61, no 4, pp. 26:1–26:55.
  • 20P. Boulet, P. Feautrier.

    Scanning Polyhedra without DO loops, in: International Conference on Parallel Architecture and Compilation Techniques (PACT'98), Paris, France, IEEE Computer Society, October 1998, pp. 4-11.
  • 21A. Darte, R. Schreiber, G. Villard.

    Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, October 2005, vol. 54, no 10, pp. 1242-1257, Special Issue: Tribute to B. Ramakrishna (Bob) Rau.
  • 22P. Feautrier.

    Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, no 5, pp. 459–487.
  • 23P. Feautrier.

    Simplification of Boolean Affine Formulas, Inria, July 2011, no RR-7689.

    http://hal.inria.fr/inria-00609519/PDF/RR-7689.pdf
  • 24P. Feautrier.

    Dataflow Analysis of Scalar and Array References, in: International Journal of Parallel Programming, February 1991, vol. 20, no 1, pp. 23–53.
  • 25P. Feautrier, A. Gamatié, L. Gonnord.

    Enhancing the Compilation of Synchronous Dataflow Programs with a Combined Numerical-Boolean Abstraction, in: CSI Journal of Computing, 2012, vol. 1, no 4, 8:86 p.
  • 26A. Gamatié, L. Gonnord.

    Static Analysis of Synchronous Programs in Signal for Efficient Design of Multi-Clocked Embedded Systems, in: International Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'11), Chicago, USA, April 2011.
  • 27A. Turjan, B. Kienhuis, E. Deprettere.

    Translating Affine Nested-Loop Programs to Process Networks, in: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), New York, NY, USA, ACM, 2004, pp. 220–229.
  • 28S. Verdoolaege, H. Nikolov, N. Todor, P. Stefanov.

    Improved Derivation of Process Networks, in: International Workshop on Optimization for DSP and Embedded Systems (ODES'06), 2006.
  • 29T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.

    Array Dataflow Analysis for Polyhedral X10 Programs, in: 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'13), Shenzhen, China, ACM, 2013.

    http://hal.inria.fr/hal-00761537
  • 30T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.

    Checking Race Freedom of Clocked X10 Programs, arXiv, 2013, no arXiv.1311.4305.

    http://hal.inria.fr/hal-00907723


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