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Bibliography

Major publications by the team in recent years
  • 1F. Blanqui, C. Helmstetter, V. Joloboff, J.-F. Monin, X. Shi.

    Designing a CPU model: from a pseudo-formal document to fast code, in: 3rd Workshop on: Rapid Simulation and Performance Evaluation: Methods and Tools, Heraklion, Greece, January 2011.

    https://hal.inria.fr/inria-00546228
  • 2D. Burger, T. M. Austin.

    The SimpleScalar Tool Set, Version 2.0, University of Wisconsin-Madison, 1997, no TR-1342.
  • 3L. Cai, D. Gajski.

    Transaction level modeling: an overview, in: CODES+ISSS '03: Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis, New York, NY, USA, ACM Press, 2003, pp. 19–24.

    http://doi.acm.org/10.1145/944645.944651
  • 4B. Cmelik, D. Keppel.

    Shade: a fast instruction-set simulator for execution profiling, in: SIGMETRICS '94: Proceedings of the 1994 ACM SIGMETRICS conference on Measurement and modeling of computer systems, New York, NY, USA, ACM, 1994, pp. 128–137.

    http://doi.acm.org/10.1145/183018.183032
  • 5C. Helmstetter, V. Joloboff.

    SimSoC: A SystemC TLM integrated ISS for full system simulation, in: APCCAS - IEEE Asia-Pacific Conference on Circuits and Systems - 2008, Macau, SAR China, IEEE (editor), IEEE, November 2008. [ DOI : 10.1109/APCCAS.2008.4746381 ]

    https://hal.inria.fr/hal-00777158
  • 6V. Joloboff, X. Zhou, C. Helmstetter, X. Gao.

    Fast Instruction Set Simulation Using LLVM-based Dynamic Translation, in: International MultiConference of Engineers and Computer Scientists 2011, Hong Kong, China, Lecture Notes in Engineering and Computer Science, Springer, March 2011, vol. 2188, pp. 212-216.

    https://hal.inria.fr/hal-00646947
  • 7J. Song, C. Helmstetter, V. Joloboff, H. Hao.

    Generation of Executable Representation for Processor Simulation with Dynamic Translation, in: 2008 International Conference on Computer Science and Software Engineering, Wuhan, China, IEEE (editor), IEEE, December 2008. [ DOI : 10.1109/CSSE.2008.635 ]

    https://hal.inria.fr/hal-00777157
  • 8E. Witchel, M. Rosenblum.

    Embra: fast and flexible machine simulation, in: SIGMETRICS '96: Proceedings of the 1996 ACM SIGMETRICS international conference on Measurement and modeling of computer systems, New York, NY, USA, ACM, 1996, pp. 68–79.

    http://doi.acm.org/10.1145/233013.233025
  • 9Z. Zuyu, V. Joloboff, X. Zhou, C. Helmstetter.

    Fast Dynamic Translation Using LLVM On Multi-Core Hosts, in: 5th Workshop on Architectural and Microarchitectural Support for Binary Translation (AMAS-BT), Portland, Oregon, United States, ACM (editor), Intel Corporation, June 2012.

    https://hal.inria.fr/hal-00777156
Publications of the year

International Conferences with Proceedings

  • 10V. Joloboff, S. Wang, Y. Deng.

    Fast approximately timed simulation, in: 2014 International Conference on Computer Science and Systems Engineering (CSSE2014), Hong Kong, SAR China, WIT Transactions on Information and Communication Technologies, WIT Press, September 2014.

    https://hal.archives-ouvertes.fr/hal-01081104
References in notes
  • 11M. Chen, X. Qin, M. Prabhat.

    Learning-oriented Property Decomposition for Automated Generation of Directed Tests, in: Journal of Electronic Testing, 2014, vol. 30, no 3, pp. 287–306.

    http://dx.doi.org/10.1007/s10836-014-5452-x
  • 12F. Fummi, G. Perbellini, M. Loghi, M. Poncino.

    ISS-centric modular HW/SW co-simulation, in: GLSVLSI '06: Proceedings of the 16th ACM Great Lakes symposium on VLSI, New York, NY, USA, ACM, 2006, pp. 31–36.

    http://doi.acm.org/10.1145/1127908.1127918
  • 13P. Gerin, S. Yoo, G. Nicolescu, A. Jerraya.

    Scalable and flexible cosimulation of SoC designs with heterogeneous multi-processor target architectures, in: ASP-DAC '01: Proceedings of the 2001 conference on Asia South Pacific design automation, New York, NY, USA, ACM, 2001, pp. 63–68.

    http://doi.acm.org/10.1145/370155.370276
  • 14C. Helmstetter, V. Joloboff, H. Xiao.

    SimSoC: A full system simulation software for embedded systems, in: OSSC'09, IEEE (editor), 2009.
  • 15R. Leupers, J. Elste, B. Landwehr.

    Generation of Interpretive and Compiled Instruction Set Simulators, in: Asia and South Pacific Design Automation Conference (ASP-DAC), 1999, pp. 339–342.
  • 16A. Li, Z. Qin, M. Chen, J. Liu.

    ADAutomation: An Activity Diagram Based Automated GUI Testing Framework for Smartphone Applications, in: Eighth International Conference on Software Security and Reliability, SERE 2014, San Francisco, California, USA, June 2014, pp. 68–77.

    http://dx.doi.org/10.1109/SERE.2014.20
  • 17W. S. Mong, J. Zhu.

    A Retargetable Micro-architecture Simulator, in: Design Automation Conference, 2003, vol. 0, 752 p.

    http://doi.ieeecomputersociety.org/10.1109/DAC.2003.1219120
  • 18A. Nohl, G. Braun, O. Schliebusch, R. Leupers, H. Meyr, A. Hoffmann.

    A universal technique for fast and flexible instruction-set architecture simulation, in: DAC '02: Proceedings of the 39th conference on Design automation, New York, NY, USA, DAC '02, ACM, 2002, pp. 22–27.

    http://doi.acm.org/10.1145/513918.513927
  • 19M. Poncino, J. Zhu.

    DynamoSim: a trace-based dynamically compiled instruction set simulator, in: ICCAD '04: Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design, Washington, DC, USA, IEEE Computer Society, 2004, pp. 131–136.

    http://dx.doi.org/10.1109/ICCAD.2004.1382557
  • 20M. Reshadi, P. Mishra, N. Dutt.

    Instruction set compiled simulation: a technique for fast and flexible instruction set simulation, in: Design Automation Conference, 2003. Proceedings, 2003, pp. 758-763.


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