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Bibliography

Major publications by the team in recent years
  • 1A. Ait El Cadi, O. Souissi, R. Ben Atitallah, N. Belanger, A. Artiba.

    Mathematical programming models for scheduling in a CPU/FPGA architecture with heterogeneous communication delays, in: Journal of Intelligent Manufacturing, April 2015, pp. 1-12. [ DOI : 10.1007/s10845-015-1075-z ]

    https://hal.inria.fr/hal-01247399
  • 2K. M. A. Ali, R. B. Atitallah, N. Fakhfakh, J.-L. Dekeyser.

    Using hardware parallelism for reducing power consumption in video streaming applications, in: 10th International Symposium on Reconfigurable Communication-centric Systems-on-Chip (ReCoSoC), 2015, Bremen, Germany, June 2015. [ DOI : 10.1109/ReCoSoC.2015.7238104 ]

    https://hal.inria.fr/hal-01247130
  • 3M. Baklouti, P. Marquet, J.-L. Dekeyser, M. Abid.

    FPGA-based many-core System-on-Chip design, in: Microprocessors and Microsystems, 2015, 38 p. [ DOI : 10.1016/j.micpro.2015.03.007 ]

    https://hal.inria.fr/hal-01144977
  • 4S. Ciobaca, D. Lucanu, V. Rusu, G. Rosu.

    A Language-Independent Proof System for Full Program Equivalence, in: Formal Aspects of Computing, 2016, vol. 28, no 3, pp. 469–497. [ DOI : 10.1007/s00165-016-0361-7 ]

    https://hal.inria.fr/hal-01245528
  • 5D. Lucanu, V. Rusu, A. Arusoaie.

    A Generic Framework for Symbolic Execution: a Coinductive Approach, in: Journal of Symbolic Computation, 2016, Accepted for publication. [ DOI : 10.1016/j.jsc.2016.07.012 ]

    https://hal.inria.fr/hal-01238696
  • 6D. Lucanu, V. Rusu, A. Arusoaie, D. Nowak.

    Verifying Reachability-Logic Properties on Rewriting-Logic Specifications, in: Logic, Rewriting, and Concurrency - Festschrift Symposium in Honor of José Meseguer, Urbana Champaign, United States, Logic, Rewriting, and Concurrency Essays Dedicated to José Meseguer on the Occasion of His 65th Birthday, Springer Verlag, September 2015, vol. 9200. [ DOI : 10.1007/978-3-319-23165-5_21 ]

    https://hal.inria.fr/hal-01158941
  • 7D. Lucanu, V. Rusu.

    Program Equivalence by Circular Reasoning, in: Formal Aspects of Computing, 2015, vol. 27, no 4, pp. 701-726. [ DOI : 10.1007/s00165-014-0319-6 ]

    https://hal.inria.fr/hal-01065830
  • 8V. Rusu, D. Lucanu, T.-F. Şerbănuţă, A. Arusoaie, A. Ştefănescu, G. Roşu.

    Language Definitions as Rewrite Theories, in: Journal of Logic and Algebraic Methods in Programming, 2016, vol. 85, no 1, pp. 98–120. [ DOI : 10.1016/j.jlamp.2015.09.001 ]

    https://hal.inria.fr/hal-01186005
  • 9V. Viswanathan, R. B. Atitallah, J.-L. Dekeyser.

    Massively Parallel Dynamically Reconfigurable Multi-FPGA Computing System , in: IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2015, Vancouver, BC , Canada, May 2015. [ DOI : 10.1109/FCCM.2015.13 ]

    https://hal.inria.fr/hal-01247116
  • 10V. Viswanathan, R. Ben Atitallah, J.-L. Dekeyser, B. Nakache, M. Nakache.

    A Parallel And Scalable Multi-FPGA based Architecture for High Performance Applications, in: The 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, FPGA '15, Monterey, California, United States, February 2015. [ DOI : 10.1145/2684746.2689115 ]

    https://hal.inria.fr/hal-01247133
Publications of the year

Articles in International Peer-Reviewed Journals

  • 11S. Ciobaca, D. Lucanu, V. Rusu, G. Rosu.

    A Language-Independent Proof System for Full Program Equivalence, in: Formal Aspects of Computing, 2016, vol. 28, no 3, pp. 469–497. [ DOI : 10.1007/s00165-016-0361-7 ]

    https://hal.inria.fr/hal-01245528
  • 12D. Lucanu, V. Rusu, A. Arusoaie.

    A Generic Framework for Symbolic Execution: a Coinductive Approach, in: Journal of Symbolic Computation, 2016, Accepted for publication. [ DOI : 10.1016/j.jsc.2016.07.012 ]

    https://hal.inria.fr/hal-01238696
  • 13J. Perier, W. Chouchene, J.-L. Dekeyser.

    Circuit Merging versus Dynamic Partial Reconfiguration -The HoMade Implementation, in: i-manager's Journal on Embedded Systems(JES), 2016.

    https://hal.inria.fr/hal-01245800
  • 14V. Rusu, D. Lucanu, T.-F. Şerbănuţă, A. Arusoaie, A. Ştefănescu, G. Roşu.

    Language Definitions as Rewrite Theories, in: Journal of Logic and Algebraic Methods in Programming, 2016, vol. 85, no 1, pp. 98–120. [ DOI : 10.1016/j.jlamp.2015.09.001 ]

    https://hal.inria.fr/hal-01186005

International Conferences with Proceedings

  • 15H. Krichene, M. Baklouti, M. Abid, P. Marquet, J.-L. Dekeyser, S. Meftali.

    SCAC-Net: Reconfigurable Interconnection Network in SCAC Massively parallel SoC, in: The 24th Euromicro International Conference on Parallel, Distributed and Network-Based Processing, Heraklion, Greece, February 2016.

    https://hal.inria.fr/hal-01247298
  • 16V. Rusu, A. Arusoaie.

    Proving Reachability-Logic Formulas Incrementally, in: 11th International Workshop on Rewriting Logic and its Applications, Eindhoven, Netherlands, April 2016, forthcoming.

    https://hal.inria.fr/hal-01282379


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