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Bibliography

Publications of the year

Articles in International Peer-Reviewed Journals

  • 1J. Bigot, V. Grandgirard, G. Latu, J.-F. Méhaut, L. F. Millani, C. Passeron, S. Q. Masnada, J. Richard, B. Videau.

    Building and Auto-Tuning Computing Kernels: Experimenting with BOAST and StarPU in the GYSELA Code, in: ESAIM: Proceedings and Surveys, October 2018, vol. 63 (2018), pp. 152 - 178. [ DOI : 10.1051/proc/201863152 ]

    https://hal.inria.fr/hal-01909325
  • 2A. El-Hokayem, Y. Falcone, M. Jaber.

    Modularizing Behavioral and Architectural Crosscutting Concerns in Formal Component-Based Systems - Application to the Behavior Interaction Priority Framework, in: Journal of Logical and Algebraic Methods in Programming, 2018, vol. 99, pp. 143–177. [ DOI : 10.1016/j.jlamp.2018.05.005 ]

    https://hal.inria.fr/hal-01796786
  • 3P. J. Pavan, R. K. Lorenzoni, V. Machado, J. Bez, E. Padoin, F. Zanon Boito, P. Navaux, J.-F. Méhaut.

    Energy Efficiency and I/O Performance of Low-Power Architectures, in: Concurrency and Computation: Practice and Experience, 2018. [ DOI : 10.1002/cpe.4948 ]

    https://hal.inria.fr/hal-01784497
  • 4P. H. Penna, A. T. A. Gomes, M. Castro, P. Plentz, H. C. D. Freitas, F. Broquedis, J.-F. Mehaut.

    A Comprehensive Performance Evaluation of the BinLPT Workload-Aware Loop Scheduler, in: Concurrency and Computation: Practice and Experience, 2019.

    https://hal.archives-ouvertes.fr/hal-01986361
  • 5M. Renard, Y. Falcone, A. Rollet, T. Jéron, H. Marchand.

    Optimal Enforcement of (Timed) Properties with Uncontrollable Events, in: Mathematical Structures in Computer Science, 2019, vol. 29, no 1, pp. 169-214. [ DOI : 10.1017/S0960129517000123 ]

    https://hal.archives-ouvertes.fr/hal-01262444
  • 6B. Videau, K. Pouget, L. Genovese, T. Deutsch, D. Komatitsch, F. Desprez, J.-F. Méhaut.

    BOAST: A metaprogramming framework to produce portable and efficient computing kernels for HPC applications, in: International Journal of High Performance Computing Applications, January 2018, vol. 32, no 1, pp. 28-44. [ DOI : 10.1177/1094342017718068 ]

    https://hal.archives-ouvertes.fr/hal-01620778
  • 7N. Zhou, G. Delaval, B. Robu, E. Rutten, J.-F. Méhaut.

    An Autonomic-Computing Approach on Mapping Threads to Multi-cores for Software Transactional Memory, in: Concurrency and Computation: Practice and Experience, September 2018, vol. 30, no 18, e4506 p. [ DOI : 10.1002/cpe.4506 ]

    https://hal.archives-ouvertes.fr/hal-01742690

Invited Conferences

  • 8Y. Falcone.

    Second School on Runtime Verification, as part of the ArVi COST Action 1402 Overview and Reflections, in: RV 2018 - 18th International Conference on Runtime Verification, Limassol, Cyprus, November 2018, pp. 1-5.

    https://hal.inria.fr/hal-01882413

International Conferences with Proceedings

  • 9C. Colombo, Y. Falcone, M. Leucker, G. Reger, C. Sanchez, G. Schneider, V. Stolz.

    COST Action IC1402 Runtime Verification beyond Monitoring, in: RV 2018 - 18th International Conference on Runtime Verification, Limassol, Cyprus, November 2018, pp. 1-8.

    https://hal.inria.fr/hal-01900195
  • 10A. El-Hokayem, Y. Falcone.

    Bringing Runtime Verification Home, in: RV 2018 - 18th International Conference on Runtime Verification, Limassol, Cyprus, November 2018, pp. 1-17.

    https://hal.inria.fr/hal-01882411
  • 11A. El-Hokayem, Y. Falcone.

    Can We Monitor All Multithreaded Programs?, in: RV 2018 - 18th International Conference on Runtime Verification, Limassol, Cyprus, November 2018, pp. 1-24.

    https://hal.inria.fr/hal-01882414
  • 12S. Fabre, J. Luís Güntzel, L. Lima Pilla, R. Netto, T. Fontana, V. Livramento.

    Enhancing Multi-Threaded Legalization Through k-d Tree Circuit Partitioning, in: SBCCI 2018 - 31st Symposium on Integrated Circuits and Systems Design, Bento Gonçalves, Brazil, August 2018, pp. 1-9.

    https://hal.inria.fr/hal-01872451
  • 13Y. Falcone, S. Krstić, G. Reger, D. Traytel.

    A Taxonomy for Classifying Runtime Verification Tools, in: RV 2018 - 18th International Conference on Runtime Verification, Limassol, Cyprus, November 2018, pp. 1-18.

    https://hal.inria.fr/hal-01882410
  • 14Y. Falcone, H. Nazarpour, M. Jaber, M. Bozga, S. Bensalem.

    Tracing Distributed Component-Based Systems, a Brief Overview, in: Proceedings of the 18th International Conference on Runtime Verification, Limassol, Cyprus, November 2018.

    https://hal.inria.fr/hal-01882412
  • 15V. Freitas, A. Santana, M. Castro, L. Lima Pilla.

    A Batch Task Migration Approach for Decentralized Global Rescheduling, in: SBAC-PAD 2018 - International Symposium on Computer Architecture and High Performance Computing, Lyon, France, September 2018, pp. 1-12.

    https://hal.inria.fr/hal-01860626
  • 16C. Hong, A. Sukumaran-Rajam, J. Kim, P. S. Rawat, S. Krishnamoorthy, L.-N. Pouchet, F. Rastello, P. Sadayappan.

    GPU Code Optimization using Abstract Kernel Emulation and Sensitivity Analysis, in: PLDI 2018 - 39th ACM SIGPLAN Conference on Programming Language Design and Implementation, Philadelphia, United States, June 2018, pp. 736-751. [ DOI : 10.1145/3192366.3192397 ]

    https://hal.inria.fr/hal-01955475
  • 17S. Kobeissi, A. Utayim, M. Jaber, Y. Falcone.

    Facilitating the Implementation of Distributed Systems with Heterogeneous Interactions, in: IFM 2018 - 14th International Conference on integrated Formal Methods, Maynooth, Ireland, September 2018, pp. 1-19.

    https://hal.inria.fr/hal-01868748
  • 18A. Ramos Carneiro, J. Luca Bez, F. Zanon Boito, B. A. Fagundes, C. Osthoff, P. Navaux.

    Collective I/O Performance on the Santos Dumont Supercomputer, in: PDP 2018 - 26th Euromicro International Conference on Parallel, Distributed and Network-based Processing, Cambridge, United Kingdom, IEEE, March 2018, pp. 45-52. [ DOI : 10.1109/PDP2018.2018.00015 ]

    https://hal.inria.fr/hal-01711359
  • 19P. Singh, A. Sukumaran-Rajam, A. Rountev, F. Rastello, L.-N. Pouchet, P. Sadayappan.

    Register Optimizations for Stencils on GPUs, in: PPoPP 2018 - 23rd ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming, Vienna, Austria, February 2018, pp. 1-15.

    https://hal.inria.fr/hal-01955542
  • 20P. Singh Rawat, A. Sukumaran-Rajam, A. Rountev, F. Rastello, L.-N. Pouchet, P. Sadayappan.

    Associative Instruction Reordering to Alleviate Register Pressure, in: SC 2018 - International Conference for High Performance Computing, Networking, Storage, and Analysis, Dallas, United States, November 2018, pp. 1-13.

    https://hal.inria.fr/hal-01956260
  • 21Y. Xia, X. Etchevers, L. Letondeur, T. Coupaye, F. Desprez.

    Combining hardware nodes and software components ordering-based heuristics for optimizing the placement of distributed IoT applications in the fog, in: SAC 2018 - 33rd Annual ACM/SIGAPP Symposium on Applied Computing, Pau, France, ACM Press, April 2018, pp. 751-760. [ DOI : 10.1145/3167132.3167215 ]

    https://hal.inria.fr/hal-01908928
  • 22Y. Xia, X. Etchevers, L. Letondeur, A. Lebre, T. Coupaye, F. Desprez.

    Combining Heuristics to Optimize and Scale the Placement of IoT Applications in the Fog, in: UCC 2018 - 11th IEEE/ACM Conference on Utility and Cloud Computing, Zurich, Switzerland, December 2018, pp. 1-11.

    https://hal.inria.fr/hal-01942097

National Conferences with Proceedings

  • 23A. Santana, V. Freitas, M. Castro, L. Lima Pilla, J.-F. Méhaut.

    Reducing Global Schedulers' Complexity Through Runtime System Decoupling, in: WSCAD 2018 - XIX Simpósio de Sistemas Computacionais de Alto Desempenho, São Paulo, Brazil, October 2018, pp. 1-12.

    https://hal.inria.fr/hal-01873526

Conferences without Proceedings

  • 24F. Bouchez-Tichadou.

    Problem solving to teach advanced algorithms in heterogeneous groups, in: ITiCSE 2018 - 23rd Annual ACM Conference on Innovation and Technology in Computer Science Education, Larnaca, Cyprus, ACM Press, July 2018, pp. 200-205. [ DOI : 10.1145/3197091.3197147 ]

    https://hal.archives-ouvertes.fr/hal-01929650
  • 26F. Trahay, M. Selva, L. Morel, K. Marquet.

    NumaMMA: NUMA MeMory Analyzer, in: ICPP 2018 - 47th International Conference on Parallel Processing, Eugene, United States, August 2018, pp. 1-10. [ DOI : 10.1145/3225058.3225094 ]

    https://hal-cea.archives-ouvertes.fr/cea-01854072

Scientific Books (or Scientific Book chapters)

  • 27E. Bartocci, Y. Falcone.

    Lectures on Runtime Verification. Introductory and Advanced Topics, LNCS, Springer, February 2018, vol. 10457, pp. 1-240. [ DOI : 10.1007/978-3-319-75632-5 ]

    https://hal.inria.fr/hal-01762298
  • 28E. Bartocci, Y. Falcone, A. Francalanza, G. Reger.

    Introduction to Runtime Verification, in: Lectures on Runtime Verification. Introductory and Advanced Topics, Lecture Notes in Computer Science, Springer, February 2018, vol. 10457, pp. 1-33. [ DOI : 10.1007/978-3-319-75632-5_1 ]

    https://hal.inria.fr/hal-01762297
  • 29Y. Falcone, L. Mariani, A. Rollet, S. Saha.

    Runtime Failure Prevention and Reaction, in: Lectures on Runtime Verification, Lecture Notes in Computer Science, Springer, February 2018, vol. 10457, pp. 103-134. [ DOI : 10.1007/978-3-319-75632-5_4 ]

    https://hal.archives-ouvertes.fr/hal-01723606

Internal Reports

  • 30F. Gruber, M. Selva, D. Sampaio, C. Guillon, L.-N. Pouchet, F. Rastello.

    Building of a Polyhedral Representation from an Instrumented Execution: Making Dynamic Analyses of non-Affine Programs Scalable, CORSE - Compiler Optimization and Run-time Systems, January 2019, no RR-9244.

    https://hal.inria.fr/hal-01967828
  • 31L. Lima Pilla.

    Basics of Vectorization for Fortran Applications, Inria Grenoble Rhône-Alpes, January 2018, no RR-9147, pp. 1-9.

    https://hal.inria.fr/hal-01688488

Other Publications

  • 32G. Berthou, A. Carer, H.-P. Charles, S. Derrien, K. Marquet, I. Miro-Panades, D. Pala, I. Puaut, F. Rastello, T. Risset, E. Rohou, G. Salagnac, O. Sentieys, B. Yarahmadi.

    The Inria ZEP project: NVRAM and Harvesting for Zero Power Computations, March 2018, 1 p, NVMW 2018 - 10th Annual Non-Volatile Memories Workshop, Poster.

    https://hal.inria.fr/hal-01941766
  • 33P. H. Penna, M. Souza, E. Podestá Júnior, B. Nascimento, M. Castro, F. Broquedis, H. Freitas, J.-F. Méhaut.

    An OS Service for Transparent Remote Memory Accesses in NoC-Based Lightweight Manycores, October 2018, 1 p, NOCS 2018 - 12th IEEE/ACM International Symposium on Networks-on-Chip, Poster. [ DOI : 10.13140/RG.2.2.13022.08000 ]

    https://hal.archives-ouvertes.fr/hal-01907003


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