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Bibliography

Major publications by the team in recent years
  • 1R. David, S. Pillement, O. Sentieys.

    Energy-Efficient Reconfigurable Processsors, in: Low Power Electronics Design, C. Piguet (editor), Computer Engineering, Vol 1, CRC Press, August 2004, chap. 20.
  • 2S. Derrien, S. Rajopadhye, P. Quinton, T. Risset.

    12, in: High-Level Synthesis From Algorithm to Digital Circuit, P. Coussy, A. Morawiec (editors), Springer Netherlands, 2008, pp. 215-230.

    http://dx.doi.org/10.1007/978-1-4020-8588-8
  • 3C. Huriaux, A. Courtay, O. Sentieys.

    Design Flow and Run-Time Management for Compressed FPGA Configurations, in: IEEE/ACM Design, Automation and Test in Europe (DATE), March 2015.

    https://hal.inria.fr/hal-01089319
  • 4J.-M. Jézéquel, B. Combemale, S. Derrien, C. Guy, S. Rajopadhye.

    Bridging the Chasm Between MDE and the World of Compilation, in: Journal of Software and Systems Modeling (SoSyM), October 2012, vol. 11, no 4, pp. 581-597. [ DOI : 10.1007/s10270-012-0266-8 ]

    https://hal.inria.fr/hal-00717219
  • 5B. Le Gal, E. Casseau, S. Huet.

    Dynamic Memory Access Management for High-Performance DSP Applications Using High-Level Synthesis, in: IEEE Transactions on VLSI Systems, 2008, vol. 16, no 11, pp. 1454-1464.
  • 6K. Martin, C. Wolinski, K. Kuchcinski, A. Floch, F. Charot.

    Constraint Programming Approach to Reconfigurable Processor Extension Generation and Application Compilation, in: ACM transactions on Reconfigurable Technology and Systems (TRETS), June 2012, vol. 5, no 2, pp. 1-38.

    http://doi.acm.org/10.1145/2209285.2209289
  • 7D. Menard, D. Chillet, F. Charot, O. Sentieys.

    Automatic Floating-point to Fixed-point Conversion for DSP Code Generation, in: Proc. ACM/IEEE CASES, October 2002.
  • 8D. Menard, O. Sentieys.

    Automatic Evaluation of the Accuracy of Fixed-point Algorithms, in: IEEE/ACM Design, Automation and Test in Europe (DATE-02), Paris, March 2002.
  • 9S. Pillement, O. Sentieys, R. David.

    DART: A Functional-Level Reconfigurable Architecture for High Energy Efficiency, in: EURASIP Journal on Embedded Systems (JES), 2008, pp. 1-13.
  • 10R. Rocher, D. Menard, O. Sentieys, P. Scalart.

    Analytical Approach for Numerical Accuracy Estimation of Fixed-Point Systems Based on Smooth Operations, in: IEEE Transactions on Circuits and Systems. Part I, Regular Papers, October 2012, vol. 59, no 10, pp. 2326 - 2339. [ DOI : 10.1109/TCSI.2012.2188938 ]

    http://hal.inria.fr/hal-00741741
  • 11C. Wolinski, M. Gokhale, K. McCabe.

    A polymorphous computing fabric, in: IEEE Micro, 2002, vol. 22, no 5, pp. 56–68.
  • 12C. Wolinski, K. Kuchcinski, E. Raffin.

    Automatic Design of Application-Specific Reconfigurable Processor Extensions with UPaK Synthesis Kernel, in: ACM Trans. on Design Automation of Elect. Syst., 2009, vol. 15, no 1, pp. 1–36.

    http://doi.acm.org/10.1145/1640457.1640458
Publications of the year

Doctoral Dissertations and Habilitation Theses

Articles in International Peer-Reviewed Journals

  • 15S.-I. Filip, A. Javeed, L. N. Trefethen.

    Smooth random functions, random ODEs, and Gaussian processes, in: SIAM Review, February 2019, vol. 61, no 1, pp. 185-205. [ DOI : 10.1137/17M1161853 ]

    https://hal.inria.fr/hal-01944992
  • 16G. Gallin, A. Tisserand.

    Generation of Finely-Pipelined GF(P ) Multipliers for Flexible Curve based Cryptography on FPGAs, in: IEEE Transactions on Computers, November 2019, vol. 68, no 11, pp. 1612-1622. [ DOI : 10.1109/TC.2019.2920352 ]

    https://hal.archives-ouvertes.fr/hal-02141260
  • 17L. Mo, A. Kritikakou, S. He.

    Energy-Aware Multiple Mobile Chargers Coordination for Wireless Rechargeable Sensor Networks, in: IEEE internet of things journal, May 2019, pp. 1-13. [ DOI : 10.1109/JIOT.2019.2918837 ]

    https://hal.inria.fr/hal-02140283
  • 18L. Mo, A. Kritikakou.

    Mapping Imprecise Computation Tasks on Cyber-Physical Systems, in: Peer-to-Peer Networking and Applications, 2019, pp. 1726–1740. [ DOI : 10.1007/s12083-019-00749-9 ]

    https://hal.archives-ouvertes.fr/hal-02397099
  • 19L. Mo, P. You, X. Cao, Y.-Q. Song, A. Kritikakou.

    Event-Driven Joint Mobile Actuators Scheduling and Control in Cyber-Physical Systems, in: IEEE Transactions on Industrial Informatics, March 2019, pp. 1-13. [ DOI : 10.1109/TII.2019.2906061 ]

    https://hal.inria.fr/hal-02080647
  • 20S. Reder, F. Kempf, H. Bucher, J. Becker, P. Alefragis, N. S. Voros, S. Skalistis, S. Derrien, I. Puaut, O. Oey, T. Stripf, C. Ferdinand, C. David, P. Ulbig, D. Mueller, U. Durak.

    Worst-Case Execution-Time-Aware Parallelization of Model-Based Avionics Applications, in: Journal of Aerospace Information Systems, November 2019, vol. 16, no 11, pp. 521-533. [ DOI : 10.2514/1.I010749 ]

    https://hal.archives-ouvertes.fr/hal-02383381

Invited Conferences

  • 21O. Sentieys.

    Playing with number for Energy Efficiency, Introduction to Approximate Computing, in: INC 2019 - IEEE International Nanodevices and Computing, Grenoble, France, IEEE, April 2019.

    https://hal.inria.fr/hal-02183527

International Conferences with Proceedings

  • 22T. Cong, F. Charot.

    Designing Application-Specific Heterogeneous Architectures from Performance Models, in: MCSoC 2019 - IEEE 13th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, Singapore, Singapore, October 2019, pp. 1-8.

    https://hal.inria.fr/hal-02289868
  • 23M. Dardaillon, S. Skalistis, I. Puaut, S. Derrien.

    Reconciling Compiler Optimizations and WCET Estimation Using Iterative Compilation, in: RTSS 2019 - 40th IEEE Real-Time Systems Symposium, Hong Kong, China, IEEE, December 2019, pp. 1-13.

    https://hal.archives-ouvertes.fr/hal-02286164
  • 24M. Gueguen, O. Sentieys, A. Termier.

    Accelerating Itemset Sampling using Satisfiability Constraints on FPGA, in: DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, IEEE, March 2019, pp. 1046-1051. [ DOI : 10.23919/DATE.2019.8714932 ]

    https://hal.inria.fr/hal-01941862
  • 25V.-P. Ha, T. Yuki, O. Sentieys.

    Towards Generic and Scalable Word-Length Optimization, in: IEEE/ACM Design Automation and Test in Europe (DATE), Grenoble, France, March 2020.

    https://hal.inria.fr/hal-02387232
  • 26J. Lee, C. Killian, S. Le Beux, D. Chillet.

    Approximate nanophotonic interconnects, in: NOCS 2019 - 13th IEEE/ACM International Symposium on Networks-on-Chip, New York, United States, ACM, October 2019, pp. 1-7. [ DOI : 10.1145/3313231.3352365 ]

    https://hal.archives-ouvertes.fr/hal-02341667
  • 27O. Matoussi, Y. Durand, O. Sentieys, A. Molnos.

    Error Analysis of the Square Root Operation for the Purpose of Precision Tuning: a Case Study on K-means, in: ASAP 2019 - 30th IEEE International Conference on Application-specific Systems, Architectures and Processors, New York, United States, IEEE, July 2019, pp. 1-8.

    https://hal.inria.fr/hal-02183945
  • 28L. Mo, A. Kritikakou, O. Sentieys.

    Approximation-aware Task Deployment on Asymmetric Multicore Processors, in: DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, IEEE, March 2019, pp. 1513-1518. [ DOI : 10.23919/DATE.2019.8715077 ]

    https://hal.inria.fr/hal-01940358
  • 29M. S. Mohammadi, M. M. Strout, T. Yuki, K. Cheshmi, E. Davis, M. Hall, M. M. Dehnavi, P. Nandy, C. Olschanowsky, A. Venkat.

    Sparse computation data dependence simplification for efficient compiler-generated inspectors, in: PLDI 2019 - 40th ACM SIGPLAN Conference on Programming Language Design and Implementation, Phoenix, United States, ACM Press, November 2019, pp. 594-609. [ DOI : 10.1145/3314221.3314646 ]

    https://hal.inria.fr/hal-02396761
  • 30R. Psiakis, A. Kritikakou, O. Sentieys, E. Casseau.

    Run-time Coarse-Grained Hardware Mitigation for Multiple Faults on VLIW Processors, in: DASIP 2019 - Conference on Design and Architectures for Signal and Image Processing, Montréal, Canada, October 2019, pp. 1-6.

    https://hal.inria.fr/hal-02344282
  • 31R. Psiakis, A. Kritikakou, O. Sentieys.

    Fine-Grained Hardware Mitigation for Multiple Long-Duration Transients on VLIW Function Units, in: DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, IEEE, March 2019, pp. 976-979. [ DOI : 10.23919/DATE.2019.8714899 ]

    https://hal.inria.fr/hal-01941860
  • 32S. Rokicki, D. Pala, J. Paturel, O. Sentieys.

    What You Simulate Is What You Synthesize: Designing a Processor Core from C++ Specifications, in: ICCAD 2019 - 38th IEEE/ACM International Conference on Computer-Aided Design, Westminster, CO, United States, IEEE, November 2019, pp. 1-8.

    https://hal.archives-ouvertes.fr/hal-02303453
  • 33S. Rokicki, E. Rohou, S. Derrien.

    Aggressive Memory Speculation in HW/SW Co-Designed Machines, in: DATE 2019 - 22nd IEEE/ACM Design, Automation and Test in Europe, Florence, Italy, IEEE, March 2019, pp. 332-335. [ DOI : 10.23919/DATE.2019.8715010 ]

    https://hal.archives-ouvertes.fr/hal-01941876
  • 34S. Rokicki.

    GhostBusters: Mitigating Spectre Attacks on a DBT-Based Processor, in: DATE 2020 - 23rd IEEE/ACM Design, Automation and Test in Europe, Grenoble, France, March 2020.

    https://hal.archives-ouvertes.fr/hal-02396631
  • 35N. Roux, B. Vrigneau, O. Sentieys.

    Improving NILM by Combining Sensor Data and Linear Programming, in: SAS 2019 - IEEE Sensors Applications Symposium, Sophia Antipolis, France, IEEE, March 2019, pp. 1-6. [ DOI : 10.1109/SAS.2019.8706021 ]

    https://hal.inria.fr/hal-02394920
  • 36B. Rouxel, S. Skalistis, S. Derrien, I. Puaut.

    Hiding Communication Delays in Contention-Free Execution for SPM-Based Multi-Core Architectures, in: ECRTS 2019 - 31st Euromicro Conference on Real-Time Systems, Stuttgart, Germany, July 2019, pp. 1-24. [ DOI : 10.4230/LIPIcs.ECRTS.2019.25 ]

    https://hal.archives-ouvertes.fr/hal-02190271
  • 37S. Skalistis, A. Kritikakou.

    Timely Fine-grained Interference-sensitive Run-time Adaptation of Time-triggered Schedules, in: RTSS 2019 - 40th IEEE Real-Time Systems Symposium, Hong Kong, China, IEEE, December 2019, pp. 1-13.

    https://hal.archives-ouvertes.fr/hal-02316392
  • 38J. O. Sosa, O. Sentieys, C. Roland, C. Killian.

    Multi-Carrier Spread-Spectrum Transceiver for WiNoC, in: NOCS 2019 - 13th IEEE/ACM International Symposium on Networks-on-Chip, New York, United States, ACM, October 2019, pp. 1-2. [ DOI : 10.1145/3313231.3352373 ]

    https://hal.inria.fr/hal-02394890
  • 39J. O. Sosa, O. Sentieys, C. Roland.

    Adaptive Transceiver for Wireless NoC to Enhance Multicast/Unicast Communication Scenarios, in: ISVLSI 2019 - IEEE Computer Society Annual Symposium on VLSI, Miami, United States, IEEE, July 2019, pp. 1-6. [ DOI : 10.1109/ISVLSI.2019.00111 ]

    https://hal.inria.fr/hal-02394902
  • 40F. de Dinechin, S.-I. Filip, L. Forget, M. Kumm.

    Table-Based versus Shift-And-Add constant multipliers for FPGAs, in: ARITH 2019 - 26th IEEE Symposium on Computer Arithmetic, Kyoto, Japan, IEEE, June 2019, pp. 1-8.

    https://hal.inria.fr/hal-02147078

Conferences without Proceedings

  • 41V.-P. Ha, T. Yuki, O. Sentieys.

    Noise Budgeting in Multiple-Kernel Word-Length Optimization, in: AxC 2019 - 4th Workshop on Approximate Computing, Florence, Italy, March 2019, pp. 1-3.

    https://hal.inria.fr/hal-02183936
  • 42S. Rokicki, D. Pala, J. Paturel, O. Sentieys.

    What You Simulate Is What You Synthesize: Design of a RISC-V Core from C++ Specifications, in: RISC-V Workshop 2019, Zurich, Switzerland, June 2019, pp. 1-2.

    https://hal.inria.fr/hal-02394911
  • 43B. Roux, M. Gautier, O. Sentieys.

    Exploration architecturale d'accélérateur pour des architectures multi-coeurs hétérogènes, in: 27ème colloque du Groupement de Recherche en Traitement du Signal et des Images, Lille, France, August 2019.

    https://hal.archives-ouvertes.fr/hal-02406976
  • 44T. Yuki.

    The Limit of Polynomials: Implications of Handelman’s Theorem for Exploring Schedules, in: IMPACT 2019 - 9th International Workshop on Polyhedral Compilation Techniques, Valencia, Spain, January 2019, pp. 1-8.

    https://hal.inria.fr/hal-02397043

Scientific Books (or Scientific Book chapters)

  • 45D. Menard, G. Caffarena, J. A. Lopez, D. Novo, O. Sentieys.

    Fixed-point refinement of digital signal processing systems, in: Digitally Enhanced Mixed Signal Systems, The Institution of Engineering and Technology, May 2019, no Chapter 1, pp. 1-37. [ DOI : 10.1049/PBCS040E_ch ]

    https://hal.inria.fr/hal-01941898
  • 46D. Ménard, G. Caffarena, J. A. Lopez, D. Novo, O. Sentieys.

    Analysis of Finite Word-Length Effects in Fixed-Point Systems, in: Handbook of Signal Processing Systems, S. S. Bhattacharyya (editor), 2019, pp. 1063-1101. [ DOI : 10.1007/978-3-319-91734-4_29 ]

    https://hal.inria.fr/hal-01941888

Other Publications

References in notes
  • 51S. Hauck, A. DeHon (editors)

    Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation, Morgan Kaufmann, 2008.
  • 52V. Baumgarte, G. Ehlers, F. May, A. Nückel, M. Vorbach, M. Weinhardt.

    PACT XPP — A Self-Reconfigurable Data Processing Architecture, in: The Journal of Supercomputing, 2003, vol. 26, no 2, pp. 167–184.
  • 53C. Beckhoff, D. Koch, J. Torresen.

    Portable module relocation and bitstream compression for Xilinx FPGAs, in: 24th Int. Conf. on Field Programmable Logic and Applications (FPL), 2014, pp. 1–8.
  • 54C. Bobda.

    Introduction to Reconfigurable Comp.: Architectures Algorithms and Applications, Springer, 2007.
  • 55S. Borkar, A. A. Chien.

    The Future of Microprocessors, in: Commun. ACM, May 2011, vol. 54, no 5, pp. 67–77.

    http://doi.acm.org/10.1145/1941487.1941507
  • 56J. M. P. Cardoso, P. C. Diniz, M. Weinhardt.

    Compiling for reconfigurable computing: A survey, in: ACM Comput. Surv., June 2010, vol. 42, 13:1 p.

    http://doi.acm.org/10.1145/1749603.1749604
  • 57K. Compton, S. Hauck.

    Reconfigurable computing: a survey of systems and software, in: ACM Comput. Surv., 2002, vol. 34, no 2, pp. 171–210.

    http://doi.acm.org/10.1145/508352.508353
  • 58J. Cong, H. Huang, C. Ma, B. Xiao, P. Zhou.

    A Fully Pipelined and Dynamically Composable Architecture of CGRA, in: IEEE Int. Symp. on Field-Program. Custom Comput. Machines (FCCM), 2014, pp. 9–16.

    http://dx.doi.org/10.1109/FCCM.2014.12
  • 59G. Constantinides, P. Cheung, W. Luk.

    Wordlength optimization for linear digital signal processing, in: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, October 2003, vol. 22, no 10, pp. 1432- 1442.
  • 60M. Coors, H. Keding, O. Luthje, H. Meyr.

    Fast Bit-True Simulation, in: Proc. ACM/IEEE Design Automation Conference (DAC), Las Vegas, june 2001, pp. 708-713.
  • 61R. H. Dennard, F. H. Gaensslen, V. L. Rideout, E. Bassous, A. R. LeBlanc.

    Design of ion-implanted MOSFET's with very small physical dimensions, in: IEEE Journal of Solid-State Circuits, 1974, vol. 9, no 5, pp. 256–268.
  • 62A. Hormati, M. Kudlur, S. Mahlke, D. Bacon, R. Rabbah.

    Optimus: efficient realization of streaming applications on FPGAs, in: Proc. ACM/IEEE CASES, 2008, pp. 41–50.
  • 63H. Kalte, M. Porrmann.

    REPLICA2Pro: Task Relocation by Bitstream Manipulation in Virtex-II/Pro FPGAs, in: 3rd Conference on Computing Frontiers (CF), 2006, pp. 403–412.
  • 64J.-E. Lee, K. Choi, N. D. Dutt.

    Compilation Approach for Coarse-Grained Reconfigurable Architectures, in: IEEE Design and Test of Computers, 2003, vol. 20, no 1, pp. 26-33.

    http://doi.ieeecomputersociety.org/10.1109/MDT.2003.1173050
  • 65H. Lee, D. Nguyen, J.-E. Lee.

    Optimizing Stream Program Performance on CGRA-based Systems, in: 52nd IEEE/ACM Design Automation Conference, 2015, pp. 110:1–110:6.

    http://doi.acm.org/10.1145/2744769.2744884
  • 66B. Mei, S. Vernalde, D. Verkest, H. De Man, R. Lauwereins.

    ADRES: An architecture with tightly coupled VLIW processor and coarse-grained reconfigurable matrix, in: Proc. FPL, Springer, 2003, pp. 61–70.
  • 67N. R. Miniskar, S. Kohli, H. Park, D. Yoo.

    Retargetable Automatic Generation of Compound Instructions for CGRA Based Reconfigurable Processor Applications, in: Proc. ACM/IEEE CASES, 2014, pp. 4:1–4:9.

    http://doi.acm.org/10.1145/2656106.2656125
  • 68Y. Park, H. Park, S. Mahlke.

    CGRA express: accelerating execution using dynamic operation fusion, in: Proc. Int. Conf. on Compilers, Architecture, and Synthesis for Embedded Systems, New York, NY, USA, CASES'09, ACM, 2009, pp. 271–280.

    http://doi.acm.org/10.1145/1629395.1629433
  • 69A. Putnam, A. Caulfield, E. Chung, D. Chiou, K. Constantinides, J. Demme, H. Esmaeilzadeh, J. Fowers, G. Gopal, J. Gray, M. Haselman, S. Hauck, S. Heil, A. Hormati, J.-Y. Kim, S. Lanka, J. Larus, E. Peterson, S. Pope, A. Smith, J. Thong, P. Xiao, D. Burger.

    A reconfigurable fabric for accelerating large-scale datacenter services, in: ACM/IEEE 41st International Symposium on Computer Architecture (ISCA), June 2014, pp. 13-24.

    http://dx.doi.org/10.1109/ISCA.2014.6853195
  • 70G. Theodoridis, D. Soudris, S. Vassiliadis.

    2, in: A survey of coarse-grain reconfigurable architectures and CAD tools, Springer Verlag, 2007.
  • 71G. Venkataramani, W. Najjar, F. Kurdahi, N. Bagherzadeh, W. Bohm, J. Hammes.

    Automatic compilation to a coarse-grained reconfigurable system-on-chip, in: ACM Trans. on Emb. Comp. Syst., 2003, vol. 2, no 4, pp. 560–589.

    http://doi.acm.org/10.1145/950162.950167


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