Section: Dissemination

Teaching - Supervision - Juries

Teaching Responsibilities

• E. Casseau is in charge of the Department of “Digital Systems” at ENSSAT Engineering Graduate School.

• D. Chillet was the responsible of the ICT Master of University of Science and Technology of Hanoi.

• C. Killian was the responsible of the second year of the ”Instrumentation” DUT at IUT, Lannion until July 2019.

• O. Sentieys is responsible of the ”Embedded Systems” major of the SISEA Master by Research.

• C. Wolinski was the Director of Esir until May 2019.

Enssat stands for ”École Nationale Supérieure des Sciences Appliquées et de Technologie” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Lannion. istic is the Electrical Engineering and Computer Science Department of the University of Rennes 1. Esir stands for ”École supérieure d'ingénieur de Rennes” and is an ”École d'Ingénieurs” of the University of Rennes 1, located in Rennes.

Teaching

• E. Casseau: signal processing, 21h, Enssat (L3)

• E. Casseau: low power design, 6h, Enssat (M1)

• E. Casseau: real time design methodology, 57h, Enssat (M1)

• E. Casseau: computer architecture, 24h, Enssat (M1)

• E. Casseau: VHDL design, 42h, Enssat (M1)

• E. Casseau: SoC and high-level synthesis, 33h, Master by Research (SISEA) and Enssat (M2)

• S. Derrien, optimizing and parallelising compilers, 14h, Master of Computer Science, istic (M2)

• S. Derrien, advanced processor architectures, 8h, Master of Computer Science, istic (M2)

• S. Derrien, high level synthesis, 20h, Master of Computer Science, istic (M2)

• S. Derrien, computer science research projects, 10h, Master of Computer Science, istic (M1)

• S. Derrien: introduction to operating systems, 8h, istic (M1)

• S. Derrien, principles of digital design, 20h, Bachelor of EE/CS, istic (L2)

• S. Derrien, computer architecture, 48h, Bachelor of Computer Science, istic (L3)

• S.I. Filip, Operating Systems, 24h, Master of Mechatronics, ENS Rennes (M2)

• F. Charot: computer architecture, 16h, Esir (L3)

• F. Charot: Computer architecture, 58h, istic (L3)

• D. Chillet: embedded processor architecture, 20h, Enssat (M1)

• D. Chillet: multimedia processor architectures, 24h, Enssat (M2)

• D. Chillet: advanced processor architectures, 20h, Enssat (M2)

• D. Chillet: micro-controller, 64h, Enssat (L3)

• D. Chillet: low-power digital CMOS circuits, 6h, Telecom Bretagne (M2)

• D. Chillet: low-power digital CMOS circuits, 4h, UBO (M2)

• C. Killian: digital electronics, 52h, iut Lannion (L1)

• C. Killian: automated measurements, 44h, iut Lannion (L2)

• A. Kritikakou: computer architecture 1, 32h, istic (L3)

• A. Kritikakou: computer architecture 2, 44h, istic (L3)

• A. Kritikakou: C and unix programming languages, 102h, istic (L3)

• A. Kritikakou: operating systems, 60h, istic (L3)

• O. Sentieys: VLSI integrated circuit design, 24h, Enssat (M1)

• O. Sentieys: VHDL and logic synthesis, 18h, Enssat (M1)

• C. Wolinski: computer architectures, 92h, Esir (L3)

• C. Wolinski: design of embedded systems, 48h, Esir (M1)

• C. Wolinski: signal, image, architecture, 26h, Esir (M1)

• C. Wolinski: programmable architectures, 10h, Esir (M1)

• C. Wolinski: component and system synthesis, 10h, Master by Research (istic ) (M2)

Supervision

• PhD: Audrey Lucas, Software support resistant to passive and active attacks for asymmetric cryptography on (very) small computation cores, Dec. 2019, A. Tisserand.

• PhD: Genevieve Ndour, Approximate computing for high energy-efficiency in internet-of-things applications, Jul. 2019, A. Tisserand, A. Molnos (CEA LETI).

• PhD in progress: Thibault Allenet, Low-Cost Neural Network Algorithms and Implementations for Temporal Sequence Processing, March 2019, O. Sentieys, O. Bichler (CEA LIST).

• PhD in progress: Minh Thanh Cong, Hardware Accelerated Simulation of Heterogeneous Multicore Platforms, May 2017, F. Charot, S. Derrien.

• PhD in progress: Minyu Cui, Energy-Quality-Time Fault Tolerant Task Mapping on Multicore Architectures, Oct. 2018, E. Casseau, A. Kritikakou.

• PhD in progress: Petr Dobias, Energy-Quality-Time Fault Tolerant Task Mapping on Multicore Architectures, Oct. 2017, E. Casseau.

• PhD in progress: Corentin Ferry, Compiler support for Runtime data compression for FPGA accelerators, Sep. 2019, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Université de Rennes 1 and Colorado State University).

• PhD in progress: Adrien Gaonac'h, Test de robustesse des systèmes embarqués par perturbation contrôlée en simulation à partir de plateformes virtuelles, Oct. 2019, D. Chillet, Yves Lhuillier (CEA LIST), Youri Helen (DGA).

• PhD in progress: Mael Gueguen, Improving the performance and energy efficiency of complex heterogeneous manycore architectures with on-chip data mining, Nov. 2016, O. Sentieys, A. Termier.

• PhD in progress: Van-Phu Ha, Application-Level Tuning of Accuracy, Nov. 2017, T. Yuki, O. Sentieys.

• PhD in progress: Jaechul Lee, Energy-Performance Trade-Off in Optical Network-on-Chip, Dec. 2018, D. Chillet, C. Killian.

• PhD in progress: Thibaut Marty, Compiler support for speculative custom hardware accelerators, Sep. 2017, T. Yuki, S. Derrien.

• PhD in progress: Romain Mercier, Fault Tolerant Network on Chip for Deep Learning Algorithms, Oct. 2018, D. Chillet, C. Killian, A. Kritikakou.

• PhD in progress: Louis Narmour, Revisiting memory allocation in tyeh polyhedral model, Sep. 2019, S. Derrien, T. Yuki and S. Rajopadhye (co-tutelle between Université de Rennes 1 and Colorado State University).

• PhD in progress: Joel Ortiz Sosa, Study and design of a digital baseband transceiver for wireless network-on-chip architectures, Nov. 2016, O. Sentieys, C. Roland (Lab-STICC).

• PhD in progress: Davide Pala, Non-Volatile Processors for Intermittently-Powered Computing Systems, Jan. 2018, O. Sentieys, I. Miro-Panades (CEA LETI).

• PhD in progress: Joseph Paturel, Design-space exploration of fault-tolerant multicores, Sep. 2018, O. Sentieys, A. Kritikakou.

• PhD in progress: Nicolas Roux, Sensor-aided Non-Intrusive Appliance Load Monitoring: Detecting Activity of Devices through Low-Cost Wireless Sensors, Oct. 2016, O. Sentieys, B. Vrigneau (IRISA/GRANIT).