SDR Technology

The different components of a radio system are illustrated in Fig. 2. Of course, all of the digital components may not be programmable, but the bigger the programmable part (dsp/fpga part on Fig. 2), the more software the radio. Dedicated ips1 are needed, for these ip it is more suitable to use the term configurable than programmable. In a typical sdr, the analog part is limited to a frequency translation down to an intermediate band which is sampled and all the signal processing is done digitally.

SDR Forum Classification

To encourage a common meaning for the term “sdr” the sdr Forum (renamed Wireless Innovation Forum (http://www.wirelessinnovation.org) proposes to distinguish five tiers:

• Tier 0 – Hardware Radio: The radio parameters cannot be changed, radio is implemented only with hardware components.
• Tier 1 – Software Controlled Radio: A radio where only the control functions are implemented in software, baseband processing is still performed in hardware, the radio is able to switch between different hardware.
• Tier 2 – Software-Defined Radio: The most popularly understood definition of sdr: the radio includes software control of modulation, bandwidth, frequency range and frequency bands. Conversion to digital domain still occurs after frequency conversion. It is currently implemented using a wide range of technologies: Asics, fpgas, dsps, etc.
• Tier 3 – Ideal Software Radio: Digital conversion occurs directly at the antenna, programmability extends to the whole system.
• Tier 4 – Ultimate Software Radio: Same reconfigurability capabilities as in Tier 3, but with a switching between two configurations in less than one millisecond.

The main restriction to build an ideal software radio is sampling rate: sampling at a high rate is not an easy task. Following the Shannon-Nyquist theorem, sampling the rf signal at a rate greater than twice the frequency of the signal is sufficient to reconstruct the signal. Sampling can be done at lower rate (decimation), but errors can be introduced (aliasing) that can be corrected by filtering (dirty radio concept). Building an sdr terminal implies a trade-of between sampling frequency and terminal complexity. For instance, sampling at 4.9 GHz would require a 12-bit resolution adc with at least 10GHz sample rate which is today not available with reasonable power consumption (several hundreds Watt).

Cognitive Radio

sdr technology enables over the air programming (Otap) which consists in describing methods for distributing new software updates through the radio interface. However, as sdr architectures are heterogeneous, a standard distribution method has not emerged yet.

Cognitive Radio is a wireless communication system that can sense the air, and decide to configure itself in a given mode, following a local or distributed decision algorithm. Although Tier 3 sdr would be an ideal platform for cognitive radio implementation, cognitive radios do not have to be sdr.

Cognitive Radio is currently a very hot research topic as show the dozens of sessions in research conferences dedicated to it. In 2009, the American National Science Foundation (nsf) held a workshop on “Future Directions in Cognitive Radio Network Research”  31. The purpose of the workshop was to explore how the transition from cognitive radios to cognitive radio networks can be made. The resulting report indicated the following: 

The report also mentioned the lack of cognitive radio testbeds and urged “The development of a set of cognitive networking test-beds that can be used to evaluate cognitive networks at various stages of their development”, which, in some sense strengthens the creation of the Socrate team and its involvement in the FIT project  27.

6.1.1 FloPoCo

• Name: Floating-Point Cores, but not only
• Keyword: Synthesizable VHDL generator
• Functional Description: The purpose of the open-source FloPoCo project is to explore the many ways in which the flexibility of the FPGA target can be exploited in the arithmetic realm.
• URL: http://flopoco.gforge.inria.fr/
• Authors: Florent de Dinechin, Bogdan Pasca, Jérémie Detrey, Radu Marius Tudoran, Sebastian Banescu, Caroline Collange, Cristian Klein-Halmaghi, Miora Maria Joldes, Xavier Pujol
• Contact: Florent de Dinechin
• Participants: Florent de Dinechin, Luc Forget
• Partners: CNRS, ENS Lyon, UCBL Lyon 1, UPVD

6.1.2 Sytare

• Keywords: Embedded systems, Operating system, Non volatile memory
• Functional Description: Sytare is an embedded operating system targeting tiny platforms with intermittent power. In order to make power failures transparent for the application, the system detects imminent failures and saves a checkpoint of program state to non-volatile memory. Hardware peripherals are also made persistent without requiring developer attention.
• URL: https://gitlab.inria.fr/citi-lab/sytare
• Publication: hal-01460699
• Authors: Tristan Delizy, Gautier Berthou, Guillaume Salagnac, Kevin Marquet, Tanguy Risset
• Contact: Guillaume Salagnac

6.1.3 NanoTracer

• Name: NanoTracer
• Keywords: Embedded systems, Power monitoring, Low power consumption
• Functional Description: NanoTracer is a high performance ammeter dedicated to power measurements for small devices. The system measures currents between 100nA and 100mA (gain is audo-adjusted dynamically) with a sampling frequency of 2Msps. Data is streamed to a PC over USB which enables long-running experiments, or just real-time visualization of data.
• URL: https://geromueller.de/nanotracer/
• Contacts: Guillaume Salagnac, Tanguy Risset

6.1.4 marto

• Name: Modern Arithmetic Tools
• Keywords: High-level synthesis, Arithmetic, FPGA
• Functional Description:

  Marto provides C++ headers to implement custom sized arithmetic operators such as:

  Custom sized posits and their environment (including the quire) Custom sized IEEE-754 numbers Custom sized Kulisch accumulators (and sums of products)

• URL: https://gitlab.inria.fr/lforget/marto
• Publication: hal-02130912v4
• Contacts: Yohann Uguen, Luc Forget, Florent de Dinechin
• Participants: Yohann Uguen, Florent de Dinechin, Luc Forget

6.1.5 hint

• Name: High-level synthesis Integer Library
• Keyword: High-level synthesis
• Functional Description: Hint is an header-only arbitrary size integer API with strong semantics for C++. Multiple backends are provided using various HLS libraries, allowing a user to write one operator and synthetize it using the main vendor tools.
• URL: https://github.com/yuguen/hint
• Publication: hal-02131798v2
• Contacts: Yohann Uguen, Luc Forget, Florent de Dinechin
• Participants: Yohann Uguen, Florent de Dinechin, Luc Forget

6.1.6 Syfala

• Name: Low-Latency Synthesizer on FPGA
• Keywords: FPGA, Compilers, High-level synthesis, Audio signal processing
• Functional Description:

  The goal of Syfala is to design an FPGA-based platform for multichannel ultra-low-latency audio Digital Signal Processing programmable at a high-level with Faust and usable for various applications ranging from sound synthesis and processing to active sound control and artificial sound field/room acoustics.

  A series of tools are currently being developed around SyFaLa. While none of them has been officially released yet, you can follow their development/evolution on the project Git repository: https://gitlab.inria.fr/risset/syfala

• URL: https://faust.grame.fr/syfala/
• Contact: Tanguy Risset

7.1.1 Wake-Up radio and wireless power transfer

We have continued to work on wake-up radio systems but particularly increased our focus on Wireless Power Transfer (WPT). We proposed to model a full transmission chain with State-Space Models 4 in order to increase the overall efficiency of a WPT system by taking into account not only the optimization of the hardware parts, but also considering the radio channel characteristics. We also have started to study the potential of distributed beamforming at the sources level 3 to increase the total harvested energy by an ideal synchronization of distributed sources, this requiring a simple but efficient feedback mechanism.

7.1.2 RFID

On RFID systems, a work on Elastic yarns to directly integrate RFID antennas in textile for passive RFID systems was done, detailing the performance of an helix antenna using such a technology 1. In parallel, we also worked on a theoretical evaluation of tag to tag communications to test the available communication quality that we can obtain depending on the distance, the placement and the position of the distant source in a scatter radio communication between two RFID tags 12.

7.1.3 Combination of spatial modulation and full-duplex

During the period, an important work was done to enhance the realism of the evaluation of combined Full-Duplex and Spatial Modulation architectures 6, 13, 15 to increase the spectral efficiency of radio links. A detailed study on the simulation of Spatial Modulation architectures was performed, taking into account the RF front-ends non-idealities to capture the behaviour of a realistic system.

7.1.4 Other related works

The bilateral collaboration with Radu Bozomitu, professor at the Technical University Gh Asachi Iasi, Romania, was initiated in 2018 during an Erasmus Mobility. Our research work focused on the implementation of an application for transmitting image notifications on the FM radio broadcasting infrastructure. This application is dedicated to warn drivers about significant road events and to increase the traffic safety and is based on the Software Defined Radio paradigm 2.

At a higher level, in the framework of the SPIE ICS chair we also published a high level survey on energy constraints for IoT devices to give some general trends and solutions to solve the problem of feeding billions of IoT devices 21.

7.2.1 The Sytare software: an operating system for transiently powered systems

In 2020 three important works were published, resulting on the research activities on Sytare. In LCTES conference 7 was proposed a formal proof of Sytare mecanism for restoring peripheral devices after power outage. In 9 was proposed a new promising checkpointing mechanism based on memory protection units (MPU) present in most modern microcontrolers. In 8 is proposed a high level way of predicting power consumption of sensor programs using peripherals. These three studies are described below.

In 8 we propose a methodology to measure, model and simulate power consumption of peripheral devices of a low-power embedded micro-controller, while keeping a reasonable development cost. This methodology is experimented against the low-power MSP-EXP430FR5739 platform that includes nonvolatile RAM for intermittent computing purposes and a handful of peripherals. The experimental measurements enable the characterization of the consumption of the peripherals, while many existing comparable studies do not provide power consumption for peripherals. These measurements are integrated into a simulator that targets low-power peripheral-intensive applications, as are most of IoT embedded programs. The accuracy of the power consumption estimation is within a 5 percent error on intermittent embedded computing using peripherals.

In 9, we propose a new incremental checkpointing mechanism supported by a common hardware component, namely a Memory Protection Unit (MPU). This mechanism leverages the hardware interrupts of the MPU: volatile RAM is read-only on boot and is progressively unlocked as soon as protection violations occur. The MPU interrupt handler is designed to flag the corresponding volatile RAM blocks as dirty, i.e., modified. When a power outage is foreseen to be imminent, the software simply has to copy the dirty blocks from volatile RAM into the non-volatile RAM to ensure application progress over power outages. We validate our approach analytically and in cycle-accurate simulation, and we show that the proposed solution can be easily implemented on real hardware.

Finaly, after a long collaboration with formal proof researchers, Delphine Demange in Rennes and Pierre-Evariste Dagan in Paris, we were able to provide the first formal modeling of transiently powered systems, this was presented at LCTES 7 and submited to ACM TOPLAS journal. The initial motivation for this work was the following: as programmers, we are ill-equipped to reason about systems where power failures are the norm rather than the exception. A first challenge consists in being able to capture all the volatile state of the application – external peripherals included – to ensure progress. A second, more fundamental, challenge consists in specifying how power failures may interact with peripheral operations. In 7, we propose a formal specification of intermittent computing with peripherals, an axiomatic model of interrupt-based checkpointing as well as its proof of correctness, machine-checked in the Coq proof assistant. We also illustrate our model with several systems proposed in the literature.

7.2.2 A high-performance ammeter for embedded systems

By the end of 2019, the socrate team designed and built a high performance ammeter dedicated to power measurements for small devices. Our prototype measures currents between 100nA and 100mA (gain is audo-adjusted dynamically) with a sampling frequency of 2Msps. Data is streamed to a PC over USB which enables long-running experiments, or just real-time visualization of data, see Fig. 4.

In 2020, Gero Müller who had started this work left Inria but continued to maintain the private git project of nanotracer (https://geromueller.de/nanotracer/). Because of Covid pandemy, the test conducted at Inria (Alexandre Abadie from the IoT SED team) has been delayed, but we are still convinced that this material can be useful to many engineers.

7.2.3 Ultra-low latency audio on FPGA

Part of the Socrate team is involved in the creation of a new Inria project focussed on Embedded Programmable Audio Systems (Emeraude team proposal) in association with the the researchers of the GRAME group (https://www.grame.fr/recherche). GRAME is a “Centre National de Création Musicale” (CNCM) organized in three departments: music production, transmission/mediation, and computer music research. Four GRAME researchers have expertise in computer science (compilation), audio DSP, digital lutherie, and human-computer interaction in general. GRAME has been leading the development of the Faust2 programming language since its creation in 2004.

Socrate and GRAME have started a collaboration through the Syfala (synthèse audio faible latence) project (https://faust.grame.fr/syfala/) whose goal is to design an FPGA-based platform for multichannel ultra-low-latency audio Digital Signal Processing (DSP), programmable at high-level with Faust and using Socrate's software FloPoCo (http://flopoco.gforge.inria.fr). A first very preliminary version of this compiler was presented at IFC2020 16 (see Fig. 5), an earlier presentation was made at PAW workshop 2019 (Programmable Audio Workshop: https://paw.grame.fr/). In septembre 2020 an ANR project (FAST: Fast Audio Signal-processing Technologies on FPGA) was accepted on this topic.

7.3.1 Embedding arithmetic optimizations in compilers

In 5, Socrate studies hardware-specific optimization opportunities currently unexploited by HLS compilers. Some of these optimizations are specializations of floating-point operations. They respect the usual semantics of the input program while other optimizations do not, assuming instead that a floating-point computation is actually intended to compute with real numbers. What matters then is to respect application-level accuracy constraints, expressed as pragmas in the source code. This provides the compiler with freedom to use non-standard arithmetic when more efficient. A source-to-source compiler is used to prototype the proposed optimizations and evaluate them on relevant benchmarks.

7.3.2 A general technique for lossless table compression

Hsiao et al. recently introduced, in the context of multipartite table methods, a lossless compression technique that replaces a table of numerical values with two smaller tables and one addition. Work in Socrate 19 has improved this technique and the resulting architecture by exposing a wider implementation space, and an exhaustive but fast algorithm exploring this space. It also shows that this technique has many more applications than originally published, and that in many of these applications the addition is for free in practice. These contributions are implemented in the open-source FloPoCo core generator, where some tables can be compressed by a factor 2.

Research Contract with Bosch 2020

In collaboration with Aric, Socrate worked with Bosch on the implementation of the square root function the context of an embedded processor.

Research Contract with SafeHear 2020

Socrate worked with recent start-up SafeHear http://safehear.fr on a an advanced professional headset, the collaboration mainly consisted in an internship advisoring.

9.1.1 Collaborations in European programs, except FP7 and H2020

New European CIG Project: IMMUNet is a European CIG project (Cost Innovators Grant) lead by University of Bologna (Italy), studying high TRL solution for Industrial Machine Monitoring with wireless sensors using LoRa physical layer and Energy harvesting.

Insa-Spie IoT Chair

The Insa-Spie IoT Chair http://www.citi-lab.fr/chairs/iot-chair/ relies on the expertise of the CITI Lab. The skills developed within the different teams of the lab integrate the study, modelling, conception and evaluation of technologies for communicating objects and dedicated network architectures. It deals with network, telecom and software matters as well as societal issues such as privacy. The chair will also lean on the skills developed at INSA Lyon or in IMU LabEx. in the framework of this chair we published a survey paper on energy consumption of IoT devices 21.

Inria Project Lab: ZEP

The ZEP project addresses the issue of designing tiny computing objects with no battery by combining non-volatile memory (NVRAM), energy harvesting, micro-architecture innovations, compiler optimizations, and static analysis. The main application target is Internet of Things (IoT) where small communicating objects will be composed of this computing part associated to a low-power wake-up radio system. The ZEP project gathers four INRIA teams that have a scientific background in architecture, compilation, operating system and low power together with the CEA Lialp and Lisan laboratories of CEA LETI & LIST.

                

The scientific work (in progress) is organized around three fields :

• specific NVRAM-based architecture
• dedicated compiler pass that computes a worst-case energy consumption
• operating system managing NVRAM and energy, ensuring memory consistency across power outages

The project is illustrated by the figure 6, where PACAP, SOCRATE, CORSE, and CAIRN are the teams involved in the project.

ANR - Imprenum

The objective of this project (INSA-Lyon, École Normale Supérieure de Lyon, CEA LETI) is to promote accuracy as a first class concern in all the levels of a computing system:

• at the hardware level, with better support for lower-than-standard and higher-than-standard precisions;
• at the level of run-time support software, in particular answering the memory management challenges entailed by adaptive precision;
• at the lower level of mathematical libraries (kernel level), for instance BLAS for linear algebra, enhancing well established libraries with precision and accuracy control;
• at the higher level of mathematical libraries (solver level, including algebraic linear solvers such as LAPACK, ad hoc steppers for Ordinary Differential Equation, eigenvalues kernels, triangularization problems for computational geometry, etc.) Here, accuracy and precision control of the lower levels should enable higher-level properties such as convergence and stability;
• at the compiler level, enhancing optimising compilers with novel optimisations related to precision and accuracy;
• at the language level, embedding accuracy specification and control in existing languages, and possibly defining domain-specific languages with accuracy-aware semantics for some classes of applications.

ADT SytaRiot

The objective of this ADT was initially to make Riot (https://www.riot-os.org/) compatible with NVRAM-based architecture, therefore to integrate Sytare with Riot (https://gitlab.inria.fr/citi-lab/sytare/) and thus open Riot to ultra low power platforms containing NVRAM, eg Texas microcontrollers Instrument MSP430FR5969.

After having completed this task, the hired engineer left and we re-orient the ADT toward the new project studied by Socrate (towards the creation of the Emeraude project): ultra low latency audio on FPGA.

Digital Hardware AI Architectures

Florent de Dinechin participates to the chair Digital Hardware AI Architectures held by Prof. Frédéric Pétrot at the Multidisciplinary Institute in Artificial Intelligence (MIAI) of Grenoble. The other participants are François Duhem (Spintec/CEA) and Fabrice Rastello (LIG/Inria), with industrial partners Google France, Kalray, STMicroelectronics, and Upmem.

This chair funds the PhD of Maxime Christ, which studies how very low-precision arithmetic formats may improve the efficiency of the learning phase of neural networks.

10.1.1 Teaching

• Tanguy Risset is professor at the Telecommunications Department of Insa Lyon.
• Florent de Dinechin is a professor at the Computer Science Department of Insa Lyon. He also teaches computer architecture at ENS-Lyon.
• Guillaume Salagnac and Kevin Marquet are associate professors at the Computer Science Department of Insa Lyon.
• Guillaume Villemaud and Florin Hutu are associate professor at the Electrical Engineering Department of Insa Lyon.

10.1.2 Supervision

• PhD in progress : Gautier Berthou : Operating system for transiently powered systems, Inria, (IPL ZEP) since 01/2018.
• PhD in progress : Luc Forget : Algèbre linéaire calculant au plus juste, ANR Imprenum, since 10/2018.
• PhD in progress :Yanni Zhou : Full Duplex and spatial modulation since 10/2018
• PhD in progress : Tarik Lassouaoui : Tag 2 Tag communication since 10/2018
• PhD in progress : Regis Rousseau : Wireless Power Transfer since 10/2018
• PhD starting : Maxime Christ : Learning in Very Low Precision since 10/2018

• PhD defended : Andrea Bocco: A variable precision hardware acceleration for scientific computing, École Doctorale MathInfo, 29/07/2020.

10.1.3 Juries

• Tanguy Risset was a member of the jury of the following theses:
  • Florian Arrestier (reviewer, INSA Rennes)
  • Guillaume Patrigeon (jury U. Montpelier)
• Florent de Dinechin was a member of the jury for
  • Andrea Bocco (INSA-Lyon)
  • Niloofar Charmchi (U. Rennes 1)

International journals

• 1 articleSofiaS. Benouakta, FlorinF. Hutu, DanieleD. Sette and YvanY. Duroc. UHF RFID Elastic Textile YarnMicrowave and Optical Technology LettersMay 2020, 1-17
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• 2 articleRadu GabrielR. Bozomitu, Florin DoruF. Hutu and NicolasN. De Pinho Ferreira. Drivers’ Warning Application Through Image Notifications on the FM Radio Broadcasting InfrastructureIEEE Access9January 2021, 13553 - 13572
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• 3 article FlorinF. Hutu, VincentV. Léchappé, GuillaumeG. Villemaud and Michaël DiM. Loreto. Study of Distributed Beamforming for Wireless Power Transfer in Presence of RF Impairments Radio Science Letters 2 2020
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• 4 article RegisR. Rousseau, GuillaumeG. Villemaud and FlorinF. Hutu. State-Space Model Representation to Characterize an Energy Harvesting Circuit Radio Science Letters 2020
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• 5 article YohannY. Uguen, FlorentF. De Dinechin, VictorV. Lezaud and StevenS. Derrien. Application-specific arithmetic in high-level synthesis tools ACM Transactions on Architecture and Code Optimization March 2020
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• 6 articleYanniY. Zhou, FlorinF. Hutu and GuillaumeG. Villemaud. Impact of Receiver Non-idealities on a Full Duplex Spatial Modulation System PerformanceIEEE wireless communications letters912July 2020, 2083-2087
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International peer-reviewed conferences

• 7 inproceedingsGautierG. Berthou, Pierre-EvaristeP.-E. Dagand, DelphineD. Demange, RémiR. Oudin and TanguyT. Risset. Intermittent Computing with Peripherals, Formally VerifiedLCTES '20: 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems ProceedingsLCTES '20 - 21st ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded SystemsLondon / Virtual, United KingdomJune 2020, 85-96
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• 8 inproceedingsGautierG. Berthou, KevinK. Marquet, TanguyT. Risset and GuillaumeG. Salagnac. Accurate Power Consumption Evaluation forPeripherals in Ultra Low-Power embedded systems2020 Global Internet of Things Summit (GIoTS)Dublin, IrelandJune 2020, 89-96
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• 9 inproceedingsGautierG. Berthou, KevinK. Marquet, TanguyT. Risset and GuillaumeG. Salagnac. MPU-based incremental checkpointing for transiently-powered systems2020 23rd Euromicro Conference on Digital System Design (DSD)Kranj, FranceAugust 2020, 89-96
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• 10 inproceedingsAndreA. Guntoro, CeciliaC. De La Parra, FarhadF. Merchant, FlorentF. De Dinechin, JohnJ. Gustafson, MartinM. Langhammer, RainerR. Leupers and SangeethS. Nambiar. Next Generation Arithmetic for Edge ComputingDATE 2020 - Design, Automation and Test in Europe ConferenceGrenoble, FranceMarch 2020, 1357-1365
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• 11 inproceedingsFlorinF. Hutu, VincentV. Léchappé, GuillaumeG. Villemaud and MichaëlM. Di Loreto. Distributed beamforming for wireless power transferURSI GASS 2020 - 33rd URSI General Assembly and Scientific SymposiumRome, ItalyAugust 2020, 1-4
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• 12 inproceedingsTarikT. Lassouaoui, FlorinF. Hutu, YvanY. Duroc and GuillaumeG. Villemaud. Theoretical BER Evaluation of Passive RFID Tag-To-Tag CommunicationsProceedings of the 2020 IEEE Radio and Wireless SymposiumIEEE RWWSan Antonio, United Stateshttps://radiowirelessweek.org/January 2020, 1-4
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• 13 inproceedingsYanniY. Zhou, FlorinF. Hutu and GuillaumeG. Villemaud. Analysis of a Spatial Modulation System over Time-varying Rician Fading Channel with a CSI DetectorRWW 2020 - IEEE Radio & Wireless Week2020 IEEE Radio and Wireless SymposiumSan Antonio, United StatesJanuary 2020, 1-5
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• 14 inproceedingsYanniY. Zhou, FlorinF. Hutu and GuillaumeG. Villemaud. Full Duplex Spatial Modulation System Performance Depending on Self-interference Cancellation AccuracyEuCAP 2020 - 14th European Conference on Antennas and PropagationProceedings of European Conference on Antennas and PropagationCopenhagen, DenmarkMarch 2020, 1-5
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• 15 inproceedings YanniY. Zhou, FlorinF. Hutu and GuillaumeG. Villemaud. Full Duplex Spatial Modulation System in presence of IQ imbalance URSI GASS 2020 Rome, Italy August 2020
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Conferences without proceedings

• 16 inproceedings TanguyT. Risset, RomainR. Michon, YannY. Orlarey, StéphaneS. Letz, GeroG. Müller and AdeyemiA. Gbadamosi. Faust2FPGA for Ultra-Low Audio Latency: Preliminary work in the Syfala project IFC2020 - Internationnal Faust Conference paris, France December 2020
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Doctoral dissertations and habilitation theses

• 17 thesis AndreaA. Bocco. A variable precision hardware acceleration for scientific computing Université de Lyon July 2020
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Reports & preprints

• 18 report PierreP. Boulet, SS. Bouveret, AA. Bugeau, EE. Frenoux, JulienJ. Lefevre, Anne-LaureA.-L. Ligozat, KevinK. Marquet, PhilippeP. Marquet, OlivierO. Michel and OO. Ridoux. Référentiel de connaissances pour un numérique éco-responsable EcoInfo September 2020
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• 19 misc MaximeM. Christ, LucL. Forget and FlorentF. de Dinechin. Lossless Differential Table Compression for Hardware Function Evaluation December 2020
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• 20 misc LaurentL. Clavier, TroelsT. Pedersen, IgnacioI. Rodriguez, MadsM. Lauridsen and MalcolmM. Egan. Experimental Evidence for Heavy Tailed Interference in the IoT March 2020
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• 21 report GuillaumeG. Villemaud and BogdanB. Stefanescu. Smart Anything - Comment alimenter des milliards d'objets connectés ? INSA LYON; SPIE ICS January 2020
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