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COMPSYS - 2011
COMPSYS - 2011


Project Team Compsys


Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography


Project Team Compsys


Members
Overall Objectives
Scientific Foundations
Application Domains
Software
New Results
Contracts and Grants with Industry
Partnerships and Cooperations
Dissemination
Bibliography




Bibliography

Publications of the year

Articles in International Peer-Reviewed Journal

  • 1B. Boissinot, P. Brisk, A. Darte, F. Rastello.

    SSI Properties Revisited, in: ACM Transactions on Embedded Computing Systems, 2011, Special Issue on Software and Compilers for Embedded Systems, to appear.

Invited Conferences

  • 2A. Darte.

    Approximations in the Polyhedral Model, in: 1st International Workshop on Polyhedral Compilation Techniques (IMPACT'11), CGO'11 Workshop, Chamonix, April 2011, Invited talk (keynote).

International Conferences with Proceedings

  • 3C. Alias, A. Darte, A. Plesco.

    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), New Orleans, USA, IEEE Computer Society, February 2012, Short paper.
  • 4C. Alias, B. Pasca, A. Plesco.

    Automatic Generation of FPGA-Specific Pipelined Accelerators, in: 7th International Symposium on Applied Reconfigurable Computing (ARC'11), Belfast, UK, Springer Verlag, March 2011, p. 53–66.
  • 5B. Boissinot, F. Brandner, A. Darte, B. Dupont de Dinechin, F. Rastello.

    A Non-Iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs, in: 9th Asian Symposium on Programming Languages and Systems (APLAS'11), Springer Verlag, December 2011.
  • 6F. Brandner, Q. Colombet.

    Copy Elimination on Data Dependence Graphs, in: Symposium on Applied Computing (SAC'12), Trento, Italy, ACM Press, March 2012, Short paper.
  • 7Q. Colombet, B. Boissinot, P. Brisk, S. Hack, F. Rastello.

    Graph Coloring and Treescan Register Allocation Using Repairing, in: International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES'11), Taipei, Taiwan, IEEE Computer Society, October 2011.
  • 8Q. Colombet, F. Brandner, A. Darte.

    Studying Optimal Spilling in the Light of SSA, in: International Conference on Compilers, Architectures, and Synthesis of Embedded Systems (CASES'11), Taipei, Taiwan, IEEE Computer Society, October 2011.
  • 9B. Combemale, L. Gonnord, V. Rusu.

    A Generic Tool for Tracing Executions Back to a DSML's Operational Semantics, in: 7th European Conference on Modelling Foundations and Applications (ECMFA 2011), Birmingham, United Kingdom, Lecture Notes in Computer Science, Springer Verlag, June 2011, vol. 6698, p. 35–51.

    http://hal.inria.fr/hal-00593425
  • 10A. Gamatie, L. Gonnord.

    Static Analysis of Synchronous Programs in Signal for Efficient Design of Multi-Clocked Embedded Systems, in: ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'11), New York, NY, USA, ACM, 2011, p. 71–80.

    http://doi.acm.org/10.1145/1967677.1967688
  • 11D. Monniaux, L. Gonnord.

    Using Bounded Model Checking to Focus Fixpoint Iterations, in: Static analysis (SAS'11), E. Yahav (editor), Lecture Notes in Computer Science, Springer Verlag, 2011, vol. 6887, p. 369–385.
  • 12M. Schoeberl, P. Schleuniger, W. Puffitsch, F. Brandner, C. W. Probst, S. Karlsson, T. Thorn.

    Towards a Time-predictable Dual-Issue Microprocessor: The Patmos Approach, in: Bringing Theory to Practice: Predictability and Performance in Embedded Systems, DATE Workshop PPES'11, Grenoble, France, March 2011, vol. 18, p. 11-21.

    http://hal.inria.fr/inria-00585320/en
  • 13A. Tavares, Q. Colombet, M. Bigonha, C. Guillon, F. M. Q. Pereira, F. Rastello.

    Decoupled Graph-Coloring Register Allocation with Hierarchical Aliasing, in: 14th International Workshop on Software and Compilers for Embedded Systems (SCOPES'11), St. Goar, Germany, ACM Press, 2011, p. 1–10.

Conferences without Proceedings

  • 15C. Alias, A. Darte, A. Plesco.

    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), Paris, January 2012.
  • 16F. Brandner, A. Darte.

    Compiler-driven Optimization of the Worst-Case Execution Time, in: Workshop “Analyse to Compile, Compile to Analyse” (ACCA'11), held with CGO'11, Chamonix, L. Gonnord, D. Monniaux (editors), April 2011.
  • 17J. Le Guen, C. Guillon, F. Rastello.

    MinIR, a Minimalistic Intermediate Representation, in: Workshop on Intermediate Representations (WIR'11), held with CGO'11, Chamonix, F. Bouchez, S. Hack, E. Visser (editors), April 2011, p. 5-12.

Scientific Books (or Scientific Book chapters)

  • 18A. Darte.

    Optimal Parallelism Detection in Nested Loops, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011, to appear.
  • 19P. Feautrier.

    Array Layout for Parallel Processing, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011, to appear.
  • 20P. Feautrier.

    Bernstein's Conditions, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011, to appear.
  • 21P. Feautrier.

    Dependences, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011, to appear.
  • 22P. Feautrier, C. Lengauer.

    The Polyhedron Model, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011, to appear.

Internal Reports

References in notes
  • 29C. Alias, A. Darte, P. Feautrier, L. Gonnord.

    Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs, in: 17th International Static Analysis Symposium (SAS'10), Perpignan, France, ACM press, September 2010, p. 117-133.
  • 30F. Bouchez, Q. Colombet, A. Darte, C. Guillon, F. Rastello.

    Parallel Copy Motion, in: 13th International Workshop on Software & Compilers for Embedded Systems (SCOPES'10), St. Goar, Germany, ACM Press, June 2010, p. 1–10.
  • 31P. Boulet, P. Feautrier.

    Scanning Polyhedra without DO loops, in: PACT'98, October 1998.
  • 32A. Darte, R. Schreiber, G. Villard.

    Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, October 2005, vol. 54, no 10, p. 1242-1257, Special Issue: Tribute to B. Ramakrishna (Bob) Rau.
  • 33B. Dupont de Dinechin, C. Monat, F. Rastello.

    Parallel Execution of Saturated Reductions, in: Workshop on Signal Processing Systems (SIPS'01), IEEE Computer Society Press, 2001, p. 373-384.
  • 34P. Feautrier.

    Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, no 5, p. 459–487.
  • 35P. Feautrier.

    Bernstein's Conditions, in: Encyclopedia of Parallel Programming, D. Padua (editor), Springer, 2011, to appear.
  • 36P. Feautrier.

    Dataflow Analysis of Scalar and Array References, in: International Journal of Parallel Programming, February 1991, vol. 20, no 1, p. 23–53.
  • 37P. Feautrier.

    Some Efficient Solutions to the Affine Scheduling Problem, Part II, Multidimensional Time, in: International Journal of Parallel Programming, December 1992, vol. 21, no 6.
  • 38A. Fraboulet, K. Godary, A. Mignotte.

    Loop Fusion for Memory Space Optimization, in: IEEE International Symposium on System Synthesis, Montréal, Canada, IEEE Press, October 2001, p. 95–100.
  • 39R. Johnson, M. Schlansker.

    Analysis of Predicated Code, in: International Workshop on Microprogramming and Microarchitecture (Micro-29), 1996.
  • 40A. Stoutchinin, F. De Ferrière.

    Efficient Static Single Assignment Form for Predication, in: International Symposium on Microarchitecture, ACM SIGMICRO and IEEE Computer Society TC-MICRO, 2001.
  • 41A. Turjan, B. Kienhuis, E. Deprettere.

    Translating affine nested-loop programs to process networks, in: International conference on Compilers, architecture, and synthesis for embedded systems (CASES'04), New York, NY, USA, ACM, 2004, p. 220–229.
  • 42S. Verdoolaege, H. Nikolov, N. Todor, P. Stefanov.

    Improved derivation of process networks, in: International Workshop on Optimization for DSP and Embedded Systems (ODES'06, 2006.