COMPSYS - 2011 - Annual activity report

COMPSYS

COMPSYS - 2011

Project Team Compsys

Members

Overall Objectives

Introduction
General Presentation
Highlights of the First 4-Years Period
Highlights

Scientific Foundations

Introduction
Back-End Code Optimizations for Embedded Processors
Program Analysis and Transformations for High-Level Synthesis

Application Domains

Application Domains

Software

Introduction
Pip
Syntol
Cl@k
PoCo
Bee
Chuba
C2fsm
RanK
Simplifiers
LAO Developments in Aggressive Compilation
LAO Developments in JIT Compilation
Low-Level Exchange Format (TireX) and Minimalist Intermediate Representation (MinIR)

New Results

Introduction
Studying Optimal Spilling in the Light of SSA
Copy Elimination on Data Dependence Graphs
Graph-Coloring and Treescan Register Allocation Using Repairing
Decoupled Graph-Coloring Register Allocation with Hierarchical Aliasing
A Non-Iterative Data-Flow Algorithm for Computing Liveness Sets in Strict SSA Programs
SSI Revisited: A Program Representation for Sparse Dataflow Analyses
Incremental Spilling
Program Analysis and Communication Optimizations for HLS
Compilation of Hardware Accelerators with Pipelined Arithmetic
FPGA Optimized Table Maker's Dilemma Architecture
Termination of Big Programs
Simplification of Boolean Affine Formulas
Retiming for Faust

Contracts and Grants with Industry

MEDIACOM: Nano2012 Project with STMicroelectronics on SSA, Register Allocation, and JIT Compilation
S2S4HLS: Nano2012 Project with STMicroelectronics on Source-to-Source Transformations for High-Level Synthesis
Creation of the Start-Up Zettice

Partnerships and Cooperations

National Initiatives
Participation in International Programs
Informal Contacts
Visits of Research Scientists
Internships

Dissemination

Animation of the Scientific Community
Teaching

Bibliography

Publications of the year
References in notes

Home | Next next

2011 Team Activity Report

COMPSYS

Compilation and Embedded Computing Systems

Research centre: Grenoble - Rhône-Alpes

In partnership with: CNRS, Université Claude Bernard (Lyon 1), Ecole normale supérieure de Lyon

In collaboration with: Laboratoire de l'Informatique du Parallélisme (LIP)

Field: Algorithmics, Programming, Software and Architecture

Theme: Architecture and Compiling

Keywords: Formal Methods, Compiling, Optimization, Embedded Systems, Hardware Accelerators, Processors