Bibliography

Major publications by the team in recent years

1A. C. Aljundi, J.-L. Dekeyser, M. T. Kechadi, I. D. Scherson.

A universal performance factor for multi-criteria evaluation of multistage interconnection networks, in: Future Generation Comp. Syst., 2006, vol. 22, n^o 7, p. 794-804.
2A. Cuccuru, J.-L. Dekeyser, P. Marquet, P. Boulet.

Towards UML 2 extensions for compact modeling of regular complex topologies, in: MODELS/UML 2005, ACM/IEEE 8th international conference on model driven engineering languages and systems, Montego Bay, Jamaica, October 2005.
3A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser, Y. Le Menach.

Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines, in: Compumag 2011, Sydney, Australia, July 2011.

http://hal.inria.fr/inria-00605645/en
4A. Gamatié, É. Rutten, H. Yu, P. Boulet, J.-L. Dekeyser.

Synchronous Modeling and Analysis of Data Intensive Applications, in: EURASIP Journal on Embedded Systems,eurasip, july 2008, vol. 2008, Article ID 561863.
5A. Gamatié.

Design of Streaming Applications on MPSoCs using Abstract Clocks, in: Design, Automation and Test in Europe Conference (DATE'2012), Dresden, Allemagne, 2012.

http://hal.inria.fr/hal-00647480/en/
6A. Gamatié, S. Le Beux, É. Piel, R. Ben Atitallah, A. Etien, P. Marquet, J.-L. Dekeyser.

A Model Driven Design Framework for Massively Parallel Embedded Systems, in: ACM Transactions on Embedded Computing Systems (TECS), 2011, vol. 10, n^o 4.

http://hal.inria.fr/inria-00637595/en
7C. Glitia, P. Boulet, E. Lenormand, M. Barreteau.

Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications, in: Journal of Systems Architecture, January 2011, vol. 57, n^o 9, p. 815-829. [ DOI : 10.1016/j.sysarc.2010.12.002 ]

http://hal.inria.fr/inria-00605069/en
8S. Le Beux, P. Marquet, J.-L. Dekeyser.

A Model Driven Co-Design Approach for High Perforamnce Embedded Systems Dedicated to Transport, in: Studies in Informatics and Control Journal, 2008, vol. 2008, n^o 4.
9P. Marquet, S. Duquennoy, S. Le Beux, S. Meftali, J.-L. Dekeyser.

Massively Parallel Processing on a Chip, in: ACM Int'l Conf. on Computing Frontiers, Ischia, Italy, May 2007.
10Santhosh Kumar. Rethinagiri, R. Ben Atitallah, S. Niar, E. Senn, J.-L. Dekeyser.

Hybrid System Level Power Consumption Estimation for 29FPGA-Based MPSoC, in: 29th IEEE International Conference on Computer Design ICCD 2011, October 2011.
11V. Rusu.

Embedding Domain-Specific Modelling Languages in Maude Specifications, in: ACM SIGSOFT Software Engineering Notes, January 2011, vol. 36, n^o 1, Extended version accepted in the Systems and Software Engineering Journal.. [ DOI : 10.1145/1921532.1921557 ]

http://hal.inria.fr/inria-00527859/en/
12C. Trabelsi, S. Meftali, R. Ben Atitallah, A. Jemai, J.-L. Dekeyser, S. Niar.

An MDE Approach for Energy Consumption Estimation in MPSoC Design, in: 2nd Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools, Italie Pisa, Jan 2010, 6 p. p.

http://hal.inria.fr/inria-00486200/en

Publications of the year

Doctoral Dissertations and Habilitation Theses

13A. Abdallah.

Conception de SoC à Base d'Horloges Abstraites : Vers l'Exploration d'Architectures en MARTE, Université des Sciences et Technologie de Lille - Lille I, March 2011.

http://hal.inria.fr/tel-00597031/en
14V. Aranega.

Traçabilité pour la mise au point de modèles et la correction de transformations, Université des Sciences et Technologie de Lille - Lille I, November 2011.

http://hal.inria.fr/tel-00597031/en

Articles in International Peer-Reviewed Journal

15G. Afonso, N. Belanger.

Making a MARTE, March 2011.
16Y. Aydi, M. Baklouti, J.-L. Dekeyser, M. Abid.

A Multi-Level Design Methodology of Multistage Interconnection Network for MPSOCs, in: International Journal of Computer Applications in Technology (IJCAT), 2011, vol. 42, n^o 1-2.

http://hal.inria.fr/inria-00563733/en
17A. Gamatié, S. Le Beux, É. Piel, R. Ben Atitallah, A. Etien, P. Marquet, J.-L. Dekeyser.

A Model Driven Design Framework for Massively Parallel Embedded Systems, in: ACM Transactions on Embedded Computing Systems (TECS), 2011, vol. 10, n^o 4.

http://hal.inria.fr/inria-00637595/en
18C. Glitia, P. Boulet, E. Lenormand, M. Barreteau.

Repetitive model refactoring strategy for the design space exploration of intensive signal processing applications, in: Journal of Systems Architecture, January 2011, vol. 57, n^o 9, p. 815-829. [ DOI : 10.1016/j.sysarc.2010.12.002 ]

http://hal.inria.fr/inria-00605069/en
19C. Pagetti, J. Forget, F. Boniol, M. Cordovilla, D. Lesens.

Multi-task implementation of multi-periodic synchronous programs, in: Discrete Event Dynamic Systems, 2011, vol. 21, n^o 3, p. 307-338.

http://hal.inria.fr/inria-00638936/en/
20L. Rose, E. Guerra, J. De Lara, A. Etien, D. Kolovos, R. F. Paige.

Generic Model Management, in: Software and Systems Modeling, 2011, in press.

http://hal.inria.fr/inria-00635200/en
21V. Rusu.

Embedding Domain-Specific Modelling Languages in Maude Specifications, in: ACM SIGSOFT Software Engineering Notes, January 2011, vol. 36, n^o 1, Extended version accepted in the Systems and Software Engineering Journal.. [ DOI : 10.1145/1921532.1921557 ]

http://hal.inria.fr/inria-00527859/en/
22A. Souissi, P. Boulet, C. Dumoulin, M. Launay.

Modélisation centrée sur les processus métier pour la génération complète de portails collaboratifs, in: Technique et Science Informatiques (TSI), November 2011.

http://hal.inria.fr/inria-00638298/en
23C. Trabelsi, R. Ben Atitallah, S. Meftali, J.-L. Dekeyser, A. Jemai.

AModel-Driven Approach for Hybrid Power Estimation in Embedded Systems Design, in: Eurasip Journal on Embedded Systems, April 2011.

http://hal.inria.fr/inria-00584360/en

Articles in National Peer-Reviewed Journal

24A. Abdallah, A. Gamatié, J.-L. Dekeyser.

Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone, in: RSTI - TSI - 30/2011. Architecture des ordinateurs, 2011, vol. 30, p. 1089 – 1114.

http://hal.inria.fr/inria-00637009/en

Invited Conferences

25S. Cherif, C. Trabelsi, S. Meftali, J.-L. Dekeyser.

High Level Design of adaptive distributed controller for Partial Dynamic reconfiguration in FPGA, in: Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, September 2011.

http://hal.inria.fr/inria-00609122/en
26M. Elhaji, B. Attia, A. Zitouni, R. Tourki, S. Meftali, J.-L. Dekeyser.

FERONOC : Flexible and extensible router implementation for diagonal mesh topology, in: Conference on Design and Architectures for Signal and Image Processing, Tampere, Finland, September 2011.

http://hal.inria.fr/inria-00609117/en

International Conferences with Proceedings

27G. Afonso, R. Ben Atitallah, N. Belanger, M. Rubio, J.-L. Dekeyser, A. Loyer.

A prototyping environment for high performance reconfigurable computing, in: 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, Montpellier, France, June 2011.
28G. Afonso, R. Ben Atitallah, N. Belanger, M. Rubio, J.-L. Dekeyser, S. Stilkerich.

Toward Generic and Adaptive Avionic Test Systems, in: NASA/ESA Conference on Adaptive Hardware and Systems, San Diego, USA, June 2011.
29G. Afonso, R. Ben Atitallah, J.-L. Dekeyser.

A Design Environment for Reconfigurable Computing Systems, in: Systems-on-Chip - System-in-Package, Lyon, France, June 2011.
30B. Anthony Jose, A. Gamatié, J. Ouy, S. Kumar Shukla.

SMT based false causal loop detection during code synthesis from Polychronous specifications, in: 9th IEEE/ACM International Conference on Formal Methods and Models for Codesign (MEMOCODE), Cambridge, United Kingdom, 2011.

http://hal.inria.fr/inria-00637574/en
31B. Combemale, L. Gonnord, V. Rusu.

A Generic Tool for Tracing Executions Back to a DSML's Operational Semantics, in: Seventh European Conference on Modelling Foundations and Applications, Birmingham, United Kingdom, Lecture Notes in Computer Science, Springer Verlag, June 2011, vol. 6698, p. 35-51.

http://hal.inria.fr/hal-00593425/en
32M. Cordovilla, F. Boniol, J. Forget, E. Noulard, C. Pagetti.

Developing critical embedded systems on multicore architectures: the Prelude-SchedMCore toolset, in: 19th International Conference on Real-Time and Network Systems, Nantes, France, Irccyn, September 2011.

http://hal.inria.fr/inria-00618587/en
33A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser.

Programming Massively Parallel Architectures using MARTE: a Case Study, in: 2nd Workshop on Model Based Engineering for Embedded Systems Design (M-BED 2011) on Date Conference 2011, Grenoble, France, March 2011.

http://hal.inria.fr/inria-00578646/en
34A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser, Y. Le Menach.

Automatic Multi-GPU Code Generation applied to Simulation of Electrical Machines, in: Compumag 2011, Sydney, Australia, July 2011.

http://hal.inria.fr/inria-00605645/en
35M. Elhaji, P. Boulet, R. Tourki, A. Zitouni, J.-L. Dekeyser, S. Meftali.

Modeling Networks-on-Chip at System Level with the MARTE UML profile, in: M-BED'2011, Grenoble, France, March 2011.

http://hal.inria.fr/inria-00569077/en
36J. Forget, E. Grolleau, C. Pagetti, P. Richard.

Dynamic Priority Scheduling of Periodic Tasks with Extended Precedences, in: IEEE 16th Conference on Emerging Technologies Factory Automation (ETFA), Toulouse, France, September 2011. [ DOI : 10.1109/ETFA.2011.6059015 ]

http://hal.inria.fr/inria-00638941/en/
37A. Gamatié.

Design of Streaming Applications on MPSoCs using Abstract Clocks, in: Design, Automation and Test in Europe Conference (DATE'2012), Dresden, Allemagne, 2012.

http://hal.inria.fr/hal-00647480/en/
38A. Gamatié, L. Gonnord.

Static analysis of synchronous programs in signal for efficient design of multi-clocked embedded systems, in: ACM SIGPLAN/SIGBED conference on Languages, compilers, and tools for embedded systems, LCTES 2011, Chicago, IL, United States, 2011, p. 71-80.

http://hal.inria.fr/inria-00586137/en
39J. Guo, A. W. De Oliveira Rodrigues, J. Thiyagalingam, F. Guyomarc'h, P. Boulet, S.-B. Scholz.

Harnessing the Power of GPUs without Losing Abstractions in SaC and ArrayOL: A Comparative Study, in: HIPS 2011, 16th International Workshop on High-Level Parallel Programming Models and Supportive Environments, Anchorage (Alaska), United States, May 2011.

http://hal.inria.fr/inria-00569100/en
40D. Monniaux, L. Gonnord.

Using Bounded Model Checking to Focus Fixpoint Iterations, in: Static analysis, Venezia, Italie, E. Yahav (editor), Lecture notes in Computer Science, Springer, 2011, vol. 6887, p. 369-385. [ DOI : 10.1007/978-3-642-23702-7_27 ]

http://hal.archives-ouvertes.fr/hal-00600087/en/
41Santhosh Kumar. Rethinagiri, R. Ben Atitallah, J.-L. Dekeyser.

A System Level Power Consumption Estimation for MPSoC, in: International Symposium on System-on-Chip 2011, October 2011.
42Santhosh Kumar. Rethinagiri, R. Ben Atitallah, S. Niar, E. Senn, J.-L. Dekeyser.

Fast and Accurate Hybrid Power Estimation Methodology for Embedded Systems , in: Conference on Design and Architectures for Signal and Image Processing (DASIP), November 2011.
44V. Rusu, D. Lucanu.

A K-Based Formal Framework for Domain-Specific Modelling Languages, in: Formal Verification of Object-Oriented Systems, Torino, Italy, October 2011.

http://hal.inria.fr/inria-00637099/en
45V. Rusu, D. Lucanu.

K Semantics for OCL - a Proposal for a Formal Definition for OCL, in: 2nd International K Workshop, Cheile Gradistei (Brasov), Roumanie, August 2011.

http://hal.inria.fr/hal-00641199/en/
46R. Wiss, F. Boniol, C. Pagetti, J. Forget.

Calcul et vérification de propriété de latence sur une spécification fonctionnelle synchrone multi-périodique, in: Approches Formelles dans l'Assistance au Développement de Logiciels (AFADL), Grenoble, 2012, to appear.

National Conferences with Proceeding

47A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser.

A Modeling Approach based on UML/MARTE for GPU Architecture, in: Symposium en Architectures nouvelles de machines (SympA'14), Saint Malo, France, May 2011.

http://hal.inria.fr/inria-00593863/en

Conferences without Proceedings

48J. Forget, E. Grolleau, C. Pagetti.

Ordonnancement de tâches périodiques avec précédences étendues sans sémaphores, in: ROADEF 2011, SAINT ETIENNE, France, École Nationale Supérieure des Mines de Saint-Étienne, March 2011.

http://hal.inria.fr/inria-00563798/en
49Santhosh Kumar. Rethinagiri, R. Ben Atitallah, S. Niar, E. Senn, J.-L. Dekeyser.

An Effective Approach for Power Consumption Modeling of Complex Processor , in: GDR SOC-SIP, June 2011.

Scientific Books (or Scientific Book chapters)

50V. Aranega, J.-M. Mottu, A. Etien, J.-L. Dekeyser.

Using Trace to Situate Errors in Model Transformations, in: Software and Data Technologies, Communications in Computer and Information Science, Springer Berlin Heidelberg, April 2011, vol. 50. [ DOI : 10.1007/978-3-642-20116-5_11 ]

http://hal.inria.fr/inria-00589253/en
51Y. Aydi, M. Baklouti, P. Marquet, J.-L. Dekeyser, M. Abid.

A Design Methodology of MIN-Based Network for MPPSoC on Reconfigurable Architecture, in: Reconfigurable Embedded Control Systems: Applications for Flexibility and Agility, M. Khalgui, H.-M. Hanisch (editors), IGI-Global, 2011, p. 209-234.

http://hal.inria.fr/inria-00563719/en
52R. Corvino, A. Gamatié, P. Boulet.

Design Space Exploration for Efficient Data Intensive Computing on SoCs, in: Handbook of Data Intensive Computing, B. Furht, A. Escalante (editors), Springer, 2011.

http://hal.inria.fr/inria-00637012/en
53J.-L. Dekeyser, A. Gamatié, S. Meftali, I. R. Quadri.

Models for Co-Design of Heterogeneous Dynamically Reconfigurable SoCs, in: Heterogeneous Embedded Systems - Design Theory and Practice, Springer, 2012, 26 p.

http://hal.inria.fr/inria-00525023/en
54A. Gamatié.

Specification of Data Intensive Applications with Data Dependency and Abstract Clocks, in: Handbook of Data Intensive Computing, B. Furht, A. Escalante (editors), Springer, 2011.

http://hal.inria.fr/inria-00637011/en/

Internal Reports

55A. Abdallah, A. Gamatié, R. Ben Atitallah, J.-L. Dekeyser.

Correct and Energy-Efficient Design of a Multimedia Application on SoCs, INRIA, August 2011, n^o RR-7715.

http://hal.inria.fr/inria-00616223/en
56A. W. De Oliveira Rodrigues, V. Aranega, A. Etien, F. Guyomarc'h, J.-L. Dekeyser.

Enabling Traceability in an MDE Approach to Improve Performance of GPU Applications, INRIA, August 2011, n^o RR-7720.

http://hal.inria.fr/inria-00617912/PDF/RR-7720.pdf
57A. W. De Oliveira Rodrigues, V. Aranega, A. Etien, F. Guyomarc'h, J.-L. Dekeyser.

Enabling Traceability in an MDE Approach to Improve Performance of GPU Applications, INRIA, August 2011, n^o RR-7720.

http://hal.inria.fr/inria-00617912/en
58A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser.

An MDE Approach for Automatic Code Generation from MARTE to OpenCL, INRIA, February 2011, n^o RR-7525.

http://hal.inria.fr/inria-00563411/en
59B. A. Jose, A. Gamatié, M. Kracht, S. K. Shukla.

Improved False Causal Loop Detection in Polychronous Specificationof Embedded Software, INRIA, 2011.

http://hal.inria.fr/inria-00637582/en

Scientific Popularization

60P. Boulet.

Modélisation et analyse de systèmes embarqués ou temps-réel avec le profil UML MARTE, in: Techniques de l'Ingenieur, February 2011, n^o IN120.

http://hal.inria.fr/inria-00587386/en

Other Publications

61A. W. De Oliveira Rodrigues, F. Guyomarc'h, J.-L. Dekeyser.

Using ArrayOL to Identify Potentially Shareable Data in Thread Work-Groups of GPUs, March 2011, Poster.

http://hal.inria.fr/inria-00594304/en/

References in notes

62The Eclipse Project, 2003.

http://www.eclipse.org
63EMF Eclipse Modeling Framework, 2007.

http://www.eclipse.org/modeling/emf
64Acceleo, 2009.

http://www.acceleo.org
65 Object Management Group, Inc. (editor)

U2 Partners' (UML 2.0): Superstructure, 2nd revised submission, January 2003.

http://www.omg.org/cgi-bin/doc?ptc/03-01-02
66 Object Management Group, Inc. (editor)

(UML 2.0): Superstructure Draft Adopted Specification, July 2003.

http://www.omg.org/cgi-bin/doc?ptc/03-07-06
67SystemC, 2002.

http://www.systemc.org/
68OpenMP Application Programme Interface, May 2005.

http://www.openmp.org/drupal/mp-documents/spec25.pdf
69A. Abdallah, A. Gamatié, J.-L. Dekeyser.

Modélisation UML/MARTE de SoC et analyse temporelle basée sur l'approche synchrone, in: SYMPosium en Architecture de machines (SympA'13), Toulouse, France, September 2009.
70A. Abdallah, A. Gamatié, J.-L. Dekeyser.

Model-Driven Design of Embedded Multimedia Applications on SoCs, in: 12th Euromicro Conference on Digital System Design (DSD2009), Patras, Greece, August 2009.
71A. Abdallah, A. Gamatié, J.-L. Dekeyser.

Correct and Energy-Efficient Design of SoCs: the H.264 Encoder Case Study, in: International Symposium on System-on-Chip (SoC'2010), Finlande Tampere, 2010.

http://hal.inria.fr/inria-00522792/en
72G. Afonso, R. B. Atitallah, N. Belanger, M. Rubio, J.-L. Dekeyser.

An Efficient Design Methodology for Hybrid Avionic Test Systems, in: IEEE Conference on Emerging Technologies and Factory Automation (ETFA), Bilbao, Spain, Sep 2010.
73A. Agrawal.

Graph Rewriting And Transformation (GReAT): A Solution For The Model Integrated Computing Bottleneck, in: 18th IEEE International Conference on Automated Software Engineering (ASE'03), 2003, p. 364-368.
74C. André, F. Mallet, R. de Simone.

Time Modeling in MARTE, in: ECSI Forum on specification & Design Languages (FDL), Barcelona Espagne, ECSI, 2007, p. 268-273.

http://hal.inria.fr/inria-00204481/en/
75V. Aranega, A. Etien, J.-L. Dekeyser.

Using an Alternative Trace for QVT, in: Workshop on Multi-Paradigm Modeling, Norvège Olso, Oct 2010.

http://hal.inria.fr/inria-00524153/en
76V. Aranega, J.-M. Mottu, A. Etien, J.-L. Dekeyser.

Traceability Mechanism for Error Localization in Model Transformation, in: ICSOFT, Bulgaria, July 2009.
77V. Aranega, J.-M. Mottu, A. Etien, J.-L. Dekeyser.

Using Traceability to Enhance Mutation Analysis Dedicated to Model Transformation, in: Workshop on Model driven Engineering Verification and Validation, Norvège Olso, Oct 2010.

http://hal.inria.fr/inria-00524150/en
78R. Bendraou, B. Combemale, X. Crégut, M.-P. Gervais.

Definition of an Executable SPEM 2.0, in: APSEC, IEEE Computer Society, 2007, p. 390-397.
79A. Benveniste, P. Caspi, S. Edwards, N. Halbwachs, P. Le Guernic, R. de Simone.

The Synchronous Languages Twelve Years Later, in: Proceedings of the IEEE, January 2003, vol. 91, n^o 1, p. 64-83.
80A. E. H. Benyamina, P. Boulet.

Multi-objective Mapping for NoC Architecture, in: Journal of Digital Information Management, December 2007, vol. 5, n^o 6, p. 378–384.
81P. Boulet.

Array-OL Revisited, Multidimensional Intensive Signal Processing Specification, INRIA, February 2007, n^o RR-6113.

http://hal.inria.fr/inria-00128840/en
82P. Boulet.

Formal Semantics of Array-OL, a Domain Specific Language for Intensive Multidimensional Signal Processing, INRIA, March 2008, n^o RR-6467.

http://hal.inria.fr/inria-00261178/en/
83P. Boulet, J.-L. Dekeyser, J.-L. Levaire, P. Marquet, J. Soula, A. Demeure.

Visual Data-parallel Programming for Signal Processing Applications, in: 9th Euromicro Workshop on Parallel and Distributed Processing, PDP 2001, Mantova, Italy, February 2001, p. 105–112.
84T. Buchmann, A. Dotor, S. Uhrig, B. Westfechtel.

Model-Driven Software Development with Graph Transformations: A Comparative Case Study, in: Applications of Graph Transformations with Industrial Relevance, Third International Symposium (AGTIVE'07), 2007, p. 345-360.
85P. Caspi, D. Pilaud, N. Halbwachs, J.A. Plaice.

Lustre: a declarative language for real-time programming, in: Proceedings of the 14th ACM SIGACT-SIGPLAN symposium on Principles of programming languages (POPL'87), ACM Press, 1987, p. 178-188.
86S. Cherif, I. R. Quadri, S. Meftali, J.-L. Dekeyser.

Modeling reconfigurable Systems-on-Chips with UML MARTE profile: an exploratory analysis, in: 13th Euromicro Conference on Digital System Design (DSD 2010), France Lille, Sep 2010.

http://hal.inria.fr/inria-00525004/en
87M. Clavel, F. Durán, S. Eker, P. Lincoln, N. Martí-Oliet, J. Meseguer, C. L. Talcott..

All About Maude, A High-Performance Logical Framework, Lecture Notes in Computer Science, Springer, 2007, vol. 4350.
88R. Corvino, A. Gamatié, P. Boulet.

Architecture Exploration for Efficient Data Transfer and Storage in Data-Parallel Applications, in: Euro-Par 2010 - Parallel Processing, P. D'Ambra, M. Guarracino, D. Talia (editors), Springer Berlin / Heidelberg, 2010, vol. 6271, p. 101–116.

http://hal.inria.fr/inria-00522786/en
89G. Csertán, G. Huszerl, I. Majzik, Z. Pap, A. Pataricza, D. Varró.

VIATRA - Visual Automated Transformations for Formal Verification and Validation of UML Models, in: 17th IEEE International Conference on Automated Software Engineering (ASE'02), 2002, p. 267-270.
90A. Demeure, A. Lafage, E. Boutillon, D. Rozzonelli, J.-C. Dufourd, J.-L. Marro.

Array-OL : Proposition d'un Formalisme Tableau pour le Traitement de Signal Multi-Dimensionnel, in: Gretsi, Juan-Les-Pins, France, September 1995.
91A. Demeure, Y. Del Gallo.

An Array Approach for Signal Processing Design, in: Sophia-Antipolis conference on Micro-Electronics (SAME 98), France, October 1998.
92P. Dumont, P. Boulet.

Transformations de code Array-OL : implémentation de la fusion de deux tâches, Laboratoire d'Informatique fondamentale de Lille et Thales Communications, October 2003.
93P. Dumont.

Étude des Transformations d'un Code Array-OL dans Gaspard, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, France, September 2002, n^o 02-11.

http://www.lifl.fr/west/publi/Dumo02rr11.ps.gz
94P. Dumont.

Spécification multidimensionnelle pour le traitement du signal systématique, Laboratoire d'informatique fondamentale de Lille, Université des sciences et technologies de Lille, 2005, (In French).
95M. Egea, V. Rusu.

Formal executable semantics for conformance in the MDE framework, in: Innivations in Software and Systems Engineering, 2010.

http://hal.inria.fr/inria-00527502/en
96A. Etien, A. Muller, T. Legrand, X. Blanc.

Combining Independent Model Transformations, in: ACM Symposium On Applied Computing (SAC), Suisse Sierre, Mar 2010.

http://hal.inria.fr/inria-00516708/en
97D. D. Gajski, R. Kuhn.

Guest Editor Introduction: New VLSI-Tools, in: IEEE Computer, December 1983, vol. 16, n^o 12, p. 11-14.
98I. Galvão, A. Goknil.

Survey of Traceability Approaches in Model-Driven Engineering, in: IEEE International Enterprise Distributed Object Computing Conference (EDOC 2007), October 2007, p. 313-326.
99A. Gamatié.

Designing Embedded Systems with the SIGNAL Programming Language, Springer, 2010.
100A. Gamatié, V. Rusu, É. Rutten.

Operational Semantics of the Marte Repetitive Structure Modeling Concepts for Data-Parallel Applications Design, in: 9th International Symposium on Parallel and Distributed Computing (ISPDC'2010), Turquie Istanbul, 2010.

http://hal.inria.fr/inria-00522787/en
101C. Glitia.

Code transformations for systematic signal processing and memory size optimizations, Université des sciences et technologies de Lille, 2006.
102F. Jouault.

Loosely Coupled Traceability for ATL, in: European Conference on Model Driven Architecture (ECMDA) workshop on traceability, 2005, p. 29–37.
103S. Le Beux, P. Marquet, J.-L. Dekeyser.

Model Driven Engineering Benefits for High Level Synthesis, INRIA, 2008, n^o 6615.

http://hal.inria.fr/inria-00311300/en/
104P. Le Guernic, J.-P. Talpin, J.-C. Le Lann.

Polychrony for System Design, in: Journal for Circuits, Systems and Computers, April 2003, vol. 12, n^o 3, p. 261–304.
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