EN FR
EN FR


previous Previous | up Home


Bibliography

Publications of the year

International Conferences with Proceedings

  • 1A. Cohen, A. Darte, P. Feautrier.

    Static Analysis of OpenStream Programs, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, Michelle Strout and Tomofumi Yuki, January 2016.

    https://hal.inria.fr/hal-01251845
  • 2A. Darte, A. Isoard, T. Yuki.

    Extended Lattice-Based Memory Allocation, in: 25th International Conference on Compiler Construction (CC'16), Barcelona, Spain, 25th International Conference on Compiler Construction (CC'16), March 2016.

    https://hal.archives-ouvertes.fr/hal-01272969
  • 3A. Darte, A. Isoard, T. Yuki.

    Liveness Analysis in Explicitly-Parallel Programs, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, Michelle Strout and Tomofumi Yuki, January 2016.

    https://hal.inria.fr/hal-01251843
  • 4G. Deest, N. Estibals, T. Yuki, S. Derrien, S. Rajopadhye.

    Towards Scalable and Efficient FPGA Stencil Accelerators, in: 6th International Workshop on Polyhedral Compilation Techniques (IMPACT'16), held with HIPEAC'16, Prague, Czech Republic, Proceedings of the IMPACT series, http://impact.gforge.inria.fr/, January 2016.

    https://hal.inria.fr/hal-01254778
  • 5X. Niu, N. Ng, S. Wang, T. Yuki, N. Yoshida, W. Luk.

    EURECA Compilation: Automatic Optimisation of Cycle-Reconfigurable Circuits, in: 26th International Conference on Field Programmable Logic and Applications, Lausanne, Switzerland, Proceedings of the 26th International Conference on Field Programmable Logic and Applications, August 2016. [ DOI : 10.1109/FPL.2016.7577359 ]

    https://hal.archives-ouvertes.fr/hal-01413307

Conferences without Proceedings

  • 6G. Deest, N. Estibals, T. Yuki, S. Derrien, S. Rajopadhye.

    Towards Scalable and Efficient FPGA Stencil Accelerators, in: IMPACT'16, Prague, Czech Republic, January 2016.

    https://hal.inria.fr/hal-01425018

Internal Reports

  • 7A. Cohen, A. Darte, P. Feautrier.

    Static Analysis of OpenStream Programs, CNRS ; Inria ; ENS Lyon, January 2016, no RR-8764, 26 p, Corresponding publication at IMPACT'16 (http://impact.gforge.inria.fr/impact2016).

    https://hal.inria.fr/hal-01184408
  • 8A. Darte, A. Isoard, T. Yuki.

    Liveness Analysis in Explicitly-Parallel Programs, CNRS ; Inria ; ENS Lyon, January 2016, no RR-8839, 25 p, Corresponding publication at IMPACT'16 (http://impact.gforge.inria.fr/impact2016).

    https://hal.inria.fr/hal-01251579
References in notes
  • 9C. Alias, A. Darte, A. Plesco.

    Optimizing Remote Accesses for Offloaded Kernels: Application to High-Level Synthesis for FPGA, in: International Conference on Design, Automation and Test in Europe (DATE'13), Grenoble, France, March 2013, pp. 575-580.
  • 10A. Darte, A. Isoard.

    Exact and Approximated Data-Reuse Optimizations for Tiling with Parametric Sizes, in: 24th International Conference on Compiler Construction (CC'15), part of ETAPS'15, London, United Kingdom, April 2015.

    https://hal.inria.fr/hal-01099017
  • 11A. Darte, R. Schreiber, G. Villard.

    Lattice-Based Memory Allocation, in: IEEE Transactions on Computers, October 2005, vol. 54, no 10, pp. 1242-1257, Special Issue: Tribute to B. Ramakrishna (Bob) Rau.
  • 12P. Feautrier.

    Scalable and Structured Scheduling, in: International Journal of Parallel Programming, October 2006, vol. 34, no 5, pp. 459–487.
  • 13P. Feautrier.

    Simplification of Boolean Affine Formulas, Inria, July 2011, no RR-7689.

    http://hal.inria.fr/inria-00609519/PDF/RR-7689.pdf
  • 14P. Feautrier.

    The Power of Polynomials, in: 5th International Workshop on Polyhedral Compilation Techniques (IMPACT'15), Amsterdam, Netherlands, A. Jimborean, A. Darte (editors), January 2015.

    https://hal.inria.fr/hal-01094787
  • 15P. Feautrier.

    Dataflow Analysis of Scalar and Array References, in: International Journal of Parallel Programming, February 1991, vol. 20, no 1, pp. 23–53.
  • 16G. Iooss.

    Detection of linear algebra operations in polyhedral programs, École normale supérieure de Lyon and Colorado State University, 2016.
  • 17A. Isoard.

    Extending Polyhedral Techniques towards Parallel Specifications and Approximations, École normale supérieure de Lyon, 2016.
  • 18H. Nazaré, I. Maffra, W. Santos, L. Oliveira, F. M. Q. Pereira, L. Gonnord.

    Validation of Memory Accesses Through Symbolic Analyses, in: ACM International Conference on Object Oriented Programming Systems Languages & Applications (OOPSLA'14), Portland, Oregon, United States, October 2014, pp. 791-809.

    https://hal.inria.fr/hal-01006209
  • 19A. Pop, A. Cohen.

    OpenStream: Expressiveness and data-flow compilation of OpenMP streaming programs, in: ACM Transactions on Architecture and Code Optimization (TACO), 2013, vol. 9, no 4, pp. 1-25.
  • 20A. Turjan, B. Kienhuis, E. Deprettere.

    Translating Affine Nested-Loop Programs to Process Networks, in: International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES'04), New York, NY, USA, ACM, 2004, pp. 220–229.
  • 21S. Verdoolaege, H. Nikolov, N. Todor, P. Stefanov.

    Improved Derivation of Process Networks, in: International Workshop on Optimization for DSP and Embedded Systems (ODES'06), 2006.
  • 22T. Yuki, P. Feautrier, S. Rajopadhye, V. Saraswat.

    Array Dataflow Analysis for Polyhedral X10 Programs, in: 18th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'13), Shenzhen, China, ACM, 2013.

    http://hal.inria.fr/hal-00761537
  • 23T. Yuki.

    Revisiting Loop Transformations with X10 Clocks, in: Proceedings of the ACM SIGPLAN Workshop on X10, Portland, OR, United States, June 2015. [ DOI : 10.1145/2771774.2771778 ]

    https://hal.inria.fr/hal-01253630


previous Previous | up Home